OSVVM: Making VHDL Transaction Based Testbenches Simple, Readable, Powerful, and Fun
Just because your design is complex does not mean your testbench needs to be. In OSVVM we have found that with proper abstractions we can create simple, readable, and powerful testbenches. In OSVVM 2016.11 we released the transaction based modeling approach we have been using for the past 20 years in our verification practice and classes. Looking at its block diagram, you will notice that its arch... »