Hassan

I was suspecting that the only method will be to use a wrapper that only uses standard logic signals and then the Platform Designer and Block Designer should not have any issue. Its amazing how poor the hardware domain EDA tools are.

Thanks Jim. Now for a simpler question.

Often the BFM is going to used with a System created using Platform Designer in Quartus or the System Builder in Vivado.

For Platform Designer this means that we create a tcl file that tells the tool what signals make up the AXI interface so it can link them with the complementing master/slave port and…[Read more]

I did need these in the past at one point but I eventually used a bridge component than converted the AHB-Lite and APB transaction into basic MM transaction just with minimum signals on the other side and I finished the work using them. Throughput did not matter much in that specific scenario since it was reading or writing some few hundreds of…[Read more]

OK, so here is how I am able to run specific test.

First I goto a suitable location where QuestaSim can save its generated files. In this case I did

cd {E:My_DesignsFPGAOsvvmLibraries}

Then I ran the following commands:

source ./Scripts/StartUp.tcl
include ./osvvm/osvvm.pro
include ./Common/Common.pro
include ./AXI4/AXI4.pro

library…[Read more]

First lets look at RunDemoTests.pro

TestSuite Axi4Full
library osvvm_TbAxi4

if {$::osvvm::ToolNameVersion ne “XSIM-2023.2”} {
include ./testbench

# Make TestCases the frame of reference
set ::osvvm::CurrentWorkingDirectory [file join $::osvvm::CurrentWorkingDirectory TestCases]
RunTest TbAxi4_DemoMemoryReadWrite1.vhd
RunTest…[Read more]

Jim I agree with you that once a test passes, it will never ever be run interactively and only in regression. I agree that the only time a test is run interactively is when a test is being developed or it fails and a closer look at waves is required.

The simple answer to the question is that to know what tests exist, we look at the test plan or…[Read more]

Thanks Jim. I know you are busy but still taking time out to write here.

With VUnit I can pass a switch to the run.py and get list of tests and then run a specific test. I can choose whether to run it in in GUI mode or batch mode. How can I do that with OSVVM AXI4 tests?

I can see that with OSVVM, each test is a different architecture of the…[Read more]

VUnit has concept of “actor”

constant my_receiver : actor_t := new_actor(“my receiver”);

This is used in message passing. So the “transaction interface” I guess contains the information that we are interested to pass e.g for MM write it would be address and data and transfer type (single vs burst) and maybe something about delay in clock cycles…[Read more]

Does OSVVM also provide message passing mechanism like the VUnit does, for creation of BFMs?

“A DDR Design cannot be built with an AXI-Interface in VHDL. The AXI is only available for Verilog.”. What does this really mean that it cannot be build with AXI-Interface in VHDL? AXI interface is just bunch of signals and the design will eventually get mapped to FPGA pins and compiled to get netlist and bitstream. Why should VHDL AXI interface…[Read more]