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Hassan
@curiousengineer
Active 2 weeks, 6 days ago
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Viewing 15 topics - 1 through 15 (of 17 total)
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Last Post
VHDL port map between std_logic_vector(0 downto 0) and std_logic
Started by:
Hassan
in:
VHDL
2
2
2 days, 16 hours ago
Eilert Backhus
Why does VHDL require explicit conversion from signed/unsigned to logic vector?
Started by:
Hassan
in:
VHDL
2
3
1 month, 1 week ago
Hassan
Convert std_logic_vector to record
Started by:
Hassan
in:
VHDL
2
5
1 month, 1 week ago
Hassan
Does VHDL contain functions like Verilog $readmemb and $readmemh?
Started by:
Hassan
in:
VHDL
2
3
1 month, 2 weeks ago
Hassan
The #if in VHDL
Started by:
Hassan
in:
VHDL
2
4
1 month, 2 weeks ago
Hassan
Mixed language simulation and synthesis support
Started by:
Hassan
in:
VHDL
2
2
1 month, 3 weeks ago
Jim Lewis
VHDL Assert that prints the entity instance name and path
Started by:
Hassan
in:
VHDL
2
3
1 month, 3 weeks ago
Jim Lewis
Bug in AxiStream Receiver for SetAxiStreamOptions that changes WaitForGet
Started by:
Hassan
in:
OSVVM
2
2
2 months, 1 week ago
Jim Lewis
Optional ports on AXI stream transmitter and receiver cannot be left unused
Started by:
Hassan
in:
OSVVM
2
8
2 months, 2 weeks ago
Hassan
Dissecting usage of DelayCoveragePkg
Started by:
Hassan
in:
OSVVM
2
4
2 months, 2 weeks ago
Jim Lewis
Dissecting the OSVVM AXI Master BFM
Started by:
Hassan
in:
OSVVM
2
12
3 months ago
Jim Lewis
Running AXI4 Simulation from OSVVM Libraries repository
1
2
Started by:
Hassan
in:
OSVVM
2
21
3 months ago
Jim Lewis
Can OSVVM Verification Component be used in VUnit based testbench?
Started by:
Hassan
in:
OSVVM
2
8
3 months ago
Jim Lewis
Log, Alert and Affirm in OSVVM
Started by:
Hassan
in:
OSVVM
2
4
3 months ago
Jim Lewis
Check functions in OSVVM
Started by:
Hassan
in:
OSVVM
2
4
3 months ago
Jim Lewis
Viewing 15 topics - 1 through 15 (of 17 total)
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