Hassan
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Hassan replied to the topic Why does VHDL require explicit conversion from signed/unsigned to logic vector? in the forum VHDL 1 month, 1 week ago
In the VHDL as it exists today, we must use numeric_std. No arithmetic is thus possible with std_logic_vector, we must use signed or unsigned.
I do not understand, what logic or arithmetic principle is broken when signed is converted to std_logic_vector implicitly or unsigned is converted to std_logic_vector implicitly.
I am merely talking about…[Read more]
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Hassan replied to the topic Convert std_logic_vector to record in the forum VHDL 1 month, 1 week ago
I am just wondering how come the big names like Siemes, Mentor Graphics e.t.c don’t fund this group. Also, the government does not seem to show any keen interest to fund this. The evolution of technology requires tools to be in place. If the industry giants don’t come together to make it happen, who else is going to make it happen?
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Hassan started the topic VHDL port map between std_logic_vector(0 downto 0) and std_logic in the forum VHDL 1 month, 2 weeks ago
When using generics to control data width of ports we could end up with std_logic_vector(0 downto 0) due to the data width being 1. When connecting this to an std_logic signal there is always an error of mismatch since there is std_logic_vector(0 downto 0) on on side and std_logic on the other side.
The way to deal with this issue is to do this…[Read more]
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Hassan replied to the topic Does VHDL contain functions like Verilog $readmemb and $readmemh? in the forum VHDL 1 month, 2 weeks ago
Thanks.
My question is actually about synthesizeable code rather than simulation and thus I have put it under VHDL rather than OSVVM.
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Hassan started the topic Does VHDL contain functions like Verilog $readmemb and $readmemh? in the forum VHDL 1 month, 2 weeks ago
Verilog/SystemVerilog (synthesis) has some functions that can read a file into a signal. These are $readmemb and $readmemh. These can both be used to easily create a ROM from file contents. As far as I know, VHDL does not contain anything along these lines that will work in synthesis. Is this true? If so, why is this so?
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Hassan started the topic Why does VHDL require explicit conversion from signed/unsigned to logic vector? in the forum VHDL 1 month, 2 weeks ago
The signed, unsigned and std_logic_vector are all ultimately based on the std_logic. Why does VHDL require explicit conversion from signed to std_logic_vector and unsigned to std_logic_vector?
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Hassan replied to the topic The #if in VHDL in the forum VHDL 1 month, 2 weeks ago
If the design has variants that are controlled using #if e.g lets say we have FEATURE1, FEATURE2, FEATURE3VER and in SystemVerilog it could be written like this:
#if FEATURE1
#endif
#if FEATURE2
#if FEATURE3VER > 2
#else
#endif
#endif
How can this be written using VHDL-2019 Conditional Analysis and how will the things used in the #if be…[Read more]
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Hassan replied to the topic Convert std_logic_vector to record in the forum VHDL 1 month, 2 weeks ago
One more thing I would say about evolving the language is that, it should have more regular updates. We had more than 10 years between VHDL 2008 and then VHDL 2019. There should be some minor updated every few years maybe 2 or 3 years. A new standard comes after more than 10 years and then the vendors take another 10 years to support more than…[Read more]
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Hassan started the topic Convert std_logic_vector to record in the forum VHDL 1 month, 2 weeks ago
Lets take an example,
constant field2_len : integer := 8;
constant field3_len : integer := 4;
constant myrecord_len : integer := 1 + field2_len + field3_len;type MyRecord is record
field1 : std_logic;
field2 : std_logic_vector(field2_len-1 downto 0);
field3 : std_logic_vector(field3_len-1 downto 0);
end record MyRecord;Now…[Read more]
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Hassan started the topic Mixed language simulation and synthesis support in the forum VHDL 1 month, 3 weeks ago
One way in which hardware engineers are suffering is that there exist more than one RTL language and both of these can be used for writing testbenches although SystemVerilog has gone ahead since it was created from Verilog by integrating Hardware Verification Language features.
A serious issue that exists is that there is no set standard (from…[Read more]
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Hassan replied to the topic The #if in VHDL in the forum VHDL 1 month, 3 weeks ago
Doesn’t that feature only work with these things:
`if (TOOL_VENDOR = “Aldec”) and (TOOL_NAME = “Riviera-PRO”) then
constant VHDL_2019_STATUS : string := “With Aldec VHDL-2019 is here” ;How will it work with things besides TOOL_VENDOR and TOOL_NAME? I do not understand why this feature has not been in VHDL from the start.
I mean using #if we…[Read more]
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Hassan started the topic The #if in VHDL in the forum VHDL 1 month, 3 weeks ago
I worked at an organization that designed very large digital designs, so large that no FPGA can fit them, millions and millions of gates. These designs had a lot of features that could be enabled or disabled using something they called configurations. A configuration would add or remove or change ports of interfaces. These would also affect other…[Read more]
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Hassan started the topic Bug in AxiStream Receiver for SetAxiStreamOptions that changes WaitForGet in the forum OSVVM 2 months, 1 week ago
I require that when the simulation starts the AxiReceiver TReady is low and it stays this way until the VC is given command to read input. This is one of the tests that I have written.
The WaitForGet is declared in line 153 of the AxiStreamReceiver. I tried to change its state using SetAxiStreamOptions(StreamRxRec, RECEIVE_READY_WAIT_FOR_GET,…[Read more]
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Hassan replied to the topic Optional ports on AXI stream transmitter and receiver cannot be left unused in the forum OSVVM 2 months, 2 weeks ago
I believe that the GetAxiStreamOptions could just be used with DEFAULT_ID, DEFAULT_DEST, DEFAULT_USER. However, I am not sure why this is not done anywhere in any testbench that comes with OSVVM.
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Hassan replied to the topic Optional ports on AXI stream transmitter and receiver cannot be left unused in the forum OSVVM 2 months, 2 weeks ago
4. The AXI stream receiver gets the ID, DEST and USER from the transmitter VC. When it gets the data, we can access what the transmitter sent it. What then is the meaning of SetAxiStreamOptions for the receiver? It should only have GetAxiStreamOptions just like it has Get and no Send command. It is a receiver after all.
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Hassan replied to the topic Optional ports on AXI stream transmitter and receiver cannot be left unused in the forum OSVVM 2 months, 2 weeks ago
The USER can be assigned as follows:
SetAxiStreamOptions(StreamTxRec, DEFAULT_USER, User);Or, within the send and sendburst commands:
Send(StreamTxRec, X”AAAA_AAAA”, ID1 & DEST1 & USER1 & ‘0’, TRUE) ;
SendBurst(StreamTxRec, 8, ID2 & DEST2 & USER2 & ‘1’) ;The check can be done like this:
Check(StreamRxRec, X”BBBB_BBBB”, ID1 & DEST1 & USER1 &…[Read more] -
Hassan replied to the topic Dissecting usage of DelayCoveragePkg in the forum OSVVM 2 months, 2 weeks ago
What is the meaning of writing something like this: GenBin(2,10,2) where the number of bins is more than one, as far as the DelayCoverage Model is concerned?
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Hassan started the topic Dissecting usage of DelayCoveragePkg in the forum OSVVM 2 months, 2 weeks ago
When I started reading the OSVVM documentation, I left the DelayCoveragePkg and the CoveragePkg for last. I had assumed that both of these are related to functional coverage which is more relevant when pseudo-random stimulus based testbench is used. It was only later that I realized that the DelayCoveragePkg serves a completely different purpose…[Read more]
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Hassan replied to the topic Optional ports on AXI stream transmitter and receiver cannot be left unused in the forum OSVVM 2 months, 3 weeks ago
I guess converting it into record is the correct way forward in that case, since that is how it works with the memory mapped AXI4 VC.
So is there any example that uses the AxiStreamGenericSignalsPkg at the moment?
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Hassan replied to the topic Optional ports on AXI stream transmitter and receiver cannot be left unused in the forum OSVVM 2 months, 3 weeks ago
One more thing. I created the dummy signals but the forgot to update this line:
constant AXI_PARAM_WIDTH : integer := TID_MAX_WIDTH + TDEST_MAX_WIDTH + TUSER_MAX_WIDTH + 1 ;
I had to add the TID_MAX_WIDTH + TDEST_MAX_WIDTH + TUSER_MAX_WIDTH back into them. Certainly the setup feels rather fidly.
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