Hassan

In the VHDL as it exists today, we must use numeric_std. No arithmetic is thus possible with std_logic_vector, we must use signed or unsigned.

I do not understand, what logic or arithmetic principle is broken when signed is converted to std_logic_vector implicitly or unsigned is converted to std_logic_vector implicitly.

I am merely talking about…[Read more]

I am just wondering how come the big names like Siemes, Mentor Graphics e.t.c don’t fund this group. Also, the government does not seem to show any keen interest to fund this. The evolution of technology requires tools to be in place. If the industry giants don’t come together to make it happen, who else is going to make it happen?

Thanks.

My question is actually about synthesizeable code rather than simulation and thus I have put it under VHDL rather than OSVVM.

If the design has variants that are controlled using #if e.g lets say we have FEATURE1, FEATURE2, FEATURE3VER and in SystemVerilog it could be written like this:

#if FEATURE1

#endif

#if FEATURE2

#if FEATURE3VER > 2

#else

#endif

#endif

How can this be written using VHDL-2019 Conditional Analysis and how will the things used in the #if be…[Read more]

One more thing I would say about evolving the language is that, it should have more regular updates. We had more than 10 years between VHDL 2008 and then VHDL 2019. There should be some minor updated every few years maybe 2 or 3 years. A new standard comes after more than 10 years and then the vendors take another 10 years to support more than…[Read more]

Doesn’t that feature only work with these things:

`if (TOOL_VENDOR = “Aldec”) and (TOOL_NAME = “Riviera-PRO”) then
constant VHDL_2019_STATUS : string := “With Aldec VHDL-2019 is here” ;

How will it work with things besides TOOL_VENDOR and TOOL_NAME? I do not understand why this feature has not been in VHDL from the start.

I mean using #if we…[Read more]

I believe that the GetAxiStreamOptions could just be used with DEFAULT_ID, DEFAULT_DEST, DEFAULT_USER. However, I am not sure why this is not done anywhere in any testbench that comes with OSVVM.

4. The AXI stream receiver gets the ID, DEST and USER from the transmitter VC. When it gets the data, we can access what the transmitter sent it. What then is the meaning of SetAxiStreamOptions for the receiver? It should only have GetAxiStreamOptions just like it has Get and no Send command. It is a receiver after all.

The USER can be assigned as follows:
SetAxiStreamOptions(StreamTxRec, DEFAULT_USER, User);

Or, within the send and sendburst commands:
Send(StreamTxRec, X”AAAA_AAAA”, ID1 & DEST1 & USER1 & ‘0’, TRUE) ;
SendBurst(StreamTxRec, 8, ID2 & DEST2 & USER2 & ‘1’) ;

The check can be done like this:
Check(StreamRxRec, X”BBBB_BBBB”, ID1 & DEST1 & USER1 &…[Read more]

What is the meaning of writing something like this: GenBin(2,10,2) where the number of bins is more than one, as far as the DelayCoverage Model is concerned?

I guess converting it into record is the correct way forward in that case, since that is how it works with the memory mapped AXI4 VC.

So is there any example that uses the AxiStreamGenericSignalsPkg at the moment?

One more thing. I created the dummy signals but the forgot to update this line:

constant AXI_PARAM_WIDTH : integer := TID_MAX_WIDTH + TDEST_MAX_WIDTH + TUSER_MAX_WIDTH + 1 ;

I had to add the TID_MAX_WIDTH + TDEST_MAX_WIDTH + TUSER_MAX_WIDTH back into them. Certainly the setup feels rather fidly.