Jim Lewis

Hi Dave,
I suspect a proper response to this may end up being a couple of blog posts in length. Lets start with a couple of references:

Comprehensive Functional Verification by Bruce Wile, John Goss, and Wolfgang Roesner covers test plans. I have not read the whole book. It is on my some day maybe list.

Peet James Snug 2000 paper on…[Read more]

The X”DEADBEUU” you are seeing is due to the masking of the lower byte.

Hi Adam,
If you are using the OSVVM Axi4Lite VC, the best way to get word addresses is to just throw away the lower address bits and do full word writes to the interface. Hence, the transaction calls would still use the addresses X”0000″, X”0004″, X”0008″, …, but since you are throwing away the lower two address bits, the memory would see it…[Read more]

Hi Adam,
Is your question, how do you connect AXI4 up to a memory that only supports word addressing? The memory would ignore the lower bits of address that correspond to the byte addresses and it would ignore strb totally. If there is a write data operation as signified by Valid and Ready, then all 32 bits get written into memory. There is…[Read more]

Hi Adam,
I am not sure what that means. What are you trying to do? In Axi4Lite, strb is a byte strobe that indicates the corresponding 8 bits is part of the write. The strb will be active when Valid is active. This may be multiple clock cycles if Ready is not also active.

Does the dpRAM only accept full 32 bit writes? Maybe this device…[Read more]

Hi Adam,
The AxiStreamTransmitter and AxiStreamReceiver both have randomization in them. There is a corresponding test case that has good examples in it, TbStream_SendGetRandom1.vhd. You can find it in OsvvmLibraries/AXI4/AxiStream/TestCases. It was just updated (meaning just before this post) to better show the different use models for…[Read more]

Oops. It took me until now to push the files to GitHub properly.

Agreed that SetDebugMode is enough for what you are doing. SetInteractiveMode = SetDebugMode + SetLogSignals + Stop Simulation when analyze or simulate error occurs.

I use SetInteractiveMode false when running a set of simulations in CI or as a regression as I want to see results from all tests, but SetInteractiveMode when debugging.

Hi Adam,
Adding random delays is a work in progress. I am posted about updates in https://osvvm.org/forums/topic/learning-osvvm-with-axi4#post-2209.

Best Regards,
Jim

Hi Adam,
I just pushed a new version of Axi4Manager.vhd with random delays. They maintain backward compatibility, and hence, you have to turn on the randomization features. No documentation yet. I still have to add random delays to Axi4Memory and Axi4Subordinate – I also need to add them to the VTI versions of the VC. Also the initial delay…[Read more]

Hi Jason,
Resolution functions are a VHDL-1987 feature. So Ashenden’s VHDL Designers Guide should have a good description of them. I will describe them briefly here too.

In VHDL-2008, element based resolution functions were extended to support array objects. So std_logic_vector is now defined as:
subtype std_logic_vector is (resolved)…[Read more]

Hi Adam,
WRT randomness in dispatching each channel, that is what I am currently working on. I added it to AxiStream in a Beta form in an earlier OSVVM release – it has changed some on the Dev branch. I will be adding it to Axi4 VC next. Each channel will be independent, so a write data should randomly happen prior to write address, as will…[Read more]

Hi Jamie,
The working library (denoted as work in VHDL) is the library into which you are currently compiling. Hence, the OSVVM packages use the name work to reference items (use work.TranscriptPkg.all).

Currently VHDL context clauses do not allow the usage of the library work. Hence, you see the usage of OSVVM there.

Diving a little…[Read more]

Hi Adam,
I have added some beta features to the 2023.04 release to see if we can address this better. As a Beta feature, there is no documentation yet – as it may change. See AxiStream/TestCases/TbStream_SendGetRandom1.vhd.

Best Regards,
Jim

Hi Adam,
Not yet. Are you interested in doing a pull request against TbUtilPkg?

Best Regards,
Jim

LibraryUnit in this case is the name which you used with simulate, hence, either the name of your testbench or configuration that runs your testbench. Often, I try to make this the same as the TextCaseName, but it does not have to be.

In VHDL, LibraryUnit is an analyzed Design Unit and from the LRM,

A design unit is
either an entity…

[Read more]

Hi Adam,
Currently the features that control these is described on pages 26 and 27 of the AxiStream_user_guide.pdf in OsvvmLibraries/Documentation. There are two controls for this:
RECEIVE_READY_BEFORE_VALID – this is true by default and allows TReady to be generated even if TValid is not asserted.
RECEIVE_READY_DELAY_CYCLES – Number of…[Read more]