Jim Lewis
Topics Engaged In
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Generate Statement Breaks UART RX VC
Started by:
in: OSVVM
- 2
- 1 week ago
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OSVVM and Cadence Xcelium
Started by:
in: OSVVM
- 2
- 3 weeks ago
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Synopsys VCS-MX
Started by:
in: OSVVM
- 3
- 1 month ago
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How to fit non-standard VCs/interfaces within the OSVVM framework
Started by:
- 2
- 1 month, 1 week ago
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randcovpoint
Started by:
in: OSVVM
- 2
- 2 months, 1 week ago
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AxiStreamReceiver: Multiple Drivers on Transaction Record.
Started by:
in: OSVVM
- 3
- 2 months, 3 weeks ago
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How does genbin work?
Started by:
in: OSVVM
- 2
- 3 months ago
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Access signals from test harness
Started by:
in: OSVVM
- 2
- 3 months, 1 week ago
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Reading *.ppm Image Files in OSVVM for Test Stimulus
Started by:
- 2
- 3 months, 3 weeks ago
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Questasim Version
Started by:
- 2
- 4 months, 1 week ago
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Compiling UART testbench.pro in Questa
Started by:
in: OSVVM
- 2
- 6 months, 2 weeks ago
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Running example test-benches with GHDL
Started by:
in: OSVVM
- 2
- 9 months, 3 weeks ago
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Vivado simulator and OSVVM
Started by:
in: OSVVM
- 2
- 10 months ago
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QuestaSim SEGV Fatal fixed in 2020.12a
Started by:
in: OSVVM
- 1
- 1 year, 4 months ago
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What do you use for test suite orchestration?
Started by:
in: OSVVM
- 2
- 1 year, 5 months ago
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Generate Statement Breaks UART RX VC
