Activity – Open Source VHDL Verification Methodology

Hassan started the topic Convert std_logic_vector to record in the forum VHDL 11 months, 1 week ago

Lets take an example,

constant field2_len : integer := 8;
constant field3_len : integer := 4;
constant myrecord_len : integer := 1 + field2_len + field3_len;

type MyRecord is record
field1 : std_logic;
field2 : std_logic_vector(field2_len-1 downto 0);
field3 : std_logic_vector(field3_len-1 downto 0);
end record MyRecord;

Now…[Read more]
Jim Lewis replied to the topic Creating Asynchronous Clocks in the forum OSVVM 11 months, 1 week ago

2024.07 updates CreateClock. They are breaking changes – meaning the way clock starts up is different. There was alot of unneeded complexity that was part of the old CreateClock that has been minimized – while still keeping clock changing at simulation cycle 0 (aka delta cycle 0).

If you want to preview it, see the Dev branch. Nominally it…[Read more]
Jim Lewis replied to the topic case splitting in the forum OSVVM 11 months, 1 week ago

Just a quick note, release 2024.07 will have a CreateJitterClock:

`
procedure CreateJitterClock (
signal Clk : inout std_logic ;
signal CoverID : inout CoverageIdType ;
constant Name : in string ;
constant Period : in time ;
constant DutyCycle : in real := 0.5 ;…[Read more]
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Jim Lewis replied to the topic Mixed language simulation and synthesis support in the forum VHDL 11 months, 1 week ago

The IEEE group that works on EDA standards in general and spawns out groups like the IEEE 1076 WG is named DASC. You can find their website here: https://dasc.org/ You can certainly work through them to form such a working group.
Jim Lewis replied to the topic VHDL Assert that prints the entity instance name and path in the forum VHDL 11 months, 1 week ago

You should be able to surround the process with
`– synthesis translate_off
process …
end process;
— synthesis translate_on
Hassan started the topic Mixed language simulation and synthesis support in the forum VHDL 11 months, 1 week ago

One way in which hardware engineers are suffering is that there exist more than one RTL language and both of these can be used for writing testbenches although SystemVerilog has gone ahead since it was created from Verilog by integrating Hardware Verification Language features.

A serious issue that exists is that there is no set standard (from…[Read more]
Hassan replied to the topic The #if in VHDL in the forum VHDL 11 months, 2 weeks ago

Doesn’t that feature only work with these things:

`if (TOOL_VENDOR = “Aldec”) and (TOOL_NAME = “Riviera-PRO”) then
constant VHDL_2019_STATUS : string := “With Aldec VHDL-2019 is here” ;

How will it work with things besides TOOL_VENDOR and TOOL_NAME? I do not understand why this feature has not been in VHDL from the start.

I mean using #if we…[Read more]
Jim Lewis replied to the topic Interrupt Handling in OSVVM AddressBus Model Independent Transactions in the forum OSVVM 11 months, 2 weeks ago

Hi Lars,
OSVVM has an InterruptHandler.vhd in OsvvmLibraries/Common/Src. It handles switching records for you. When there is no interrupt pending, it connects the transaction record of TransRec to the AddressBus VC (such as Axi4Manager or Axi4LiteManager). When an interrupt is pending it connects the InterruptRec to the AddressBusVC.

The…[Read more]
Jim Lewis replied to the topic The #if in VHDL in the forum VHDL 11 months, 2 weeks ago

Hi Hassan,
It is part of VHDL-2019. It is called Conditional Analysis. I have heard that vendors support it in older revisions.

For details, see my presentation, VHDL-2019: Just the New Stuff Part 1: Interfaces, Conditional Analysis, File IO, and Environment. I did this through Aldec as one of their events. You should be able to register…[Read more]
Jim Lewis replied to the topic AxiStreamReceiver: Multiple Drivers on Transaction Record. in the forum OSVVM 11 months, 2 weeks ago

Hi Lars,
OSVVM has an InterruptHandler.vhd in OsvvmLibraries/Common/Src. It handles switching records for you. When there is no interrupt pending, it connects the transaction record of TransRec to the AddressBus VC (such as Axi4Manager or Axi4LiteManager). When an interrupt is pending it connects the InterruptRec to the AddressBusVC.

The…[Read more]
Hassan started the topic The #if in VHDL in the forum VHDL 11 months, 2 weeks ago

I worked at an organization that designed very large digital designs, so large that no FPGA can fit them, millions and millions of gates. These designs had a lot of features that could be enabled or disabled using something they called configurations. A configuration would add or remove or change ports of interfaces. These would also affect other…[Read more]
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l1234 started the topic Interrupt Handling in OSVVM AddressBus Model Independent Transactions in the forum OSVVM 11 months, 2 weeks ago

Moin Jim,
I have a slightly different problem with “Multiple Drivers on Transaction Record”:
I have created a VIP block acting as an interrupt service routine, e.g. clearing the detected interrupt bits on interrupt occurrence, just like a SW driver would do.
A parallel testcase process is running. Both parts access the same register space.
So, I…[Read more]
Steve replied to the topic Ethernet VIP Documentation in the forum OSVVM 11 months, 2 weeks ago

OK Thanks.
Jim Lewis replied to the topic Ethernet VIP Documentation in the forum OSVVM 11 months, 2 weeks ago

Hi Steve,
No documentation yet. Set the test case that is for now in TestStandAlone/Tb_xMii.vhd.

The VC are streaming interfaces that accept SendBurst and GetBurst.

Best Regards,
Jim
Steve started the topic Ethernet VIP Documentation in the forum OSVVM 11 months, 2 weeks ago

I don’t see any documentation for the Ethernet VIP. Just wondering if this exists somewhere.
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