Activity

One more thing. I created the dummy signals but the forgot to update this line:

constant AXI_PARAM_WIDTH : integer := TID_MAX_WIDTH + TDEST_MAX_WIDTH + TUSER_MAX_WIDTH + 1 ;

I had to add the TID_MAX_WIDTH + TDEST_MAX_WIDTH + TUSER_MAX_WIDTH back into them. Certainly the setup feels rather fidly.

I have used these 3 attributes in a process but it seems that Quartus synthesis does not support any of them at all. It just gives error “predefined attribute … is not supported”

p_assert_generics: process
begin

report p_assert_generics’simple_name severity warning;
report p_assert_generics’instance_name severity warning;…[Read more]

This is just the VHDL signal use model when reading it after assigning it in a process. Since RTL does not allow wait for 0 ns, it is limited to testbenches.

Verilog assignments have the same sort of issue.

Hi Ajeetha,
Next time please provide a complete testable example, such as I have provided below. Try running this.

library osvvm ;
context osvvm.OsvvmContext ;
use osvvm.ScoreboardPkg_int.all ;

ControlProc :…[Read more]

That worked, thanks. Can we bukcteize this as potential race condition?

Do:
stim : process
begin
SB_int <= NewID("COUNT_SB");
wait for 0 ns; -- let SB_int to update
report ("SB_int: " & integer'image(SB_int.Id));
i_up_or_down <= '0';
push(SB_int, 2);
. . .

I guessed that and did add a 1ns delay before calling NewID – please see the stim process above. Still no luck!

Thanks

Hi Ajeetha,
Nope. That is integer’left.

Put a “wait for 0 ns” before reading the signal. That allows a simulation cycle to go by and the signal to update to the value assigned by NewID.

Jim