Author: Jim Lewis
VHDL-2019 Interfaces & OSVVM Interfaces
Ever wanted to encapsulate all the signals of an interface (such as AXI4Lite, I2C, …) into a single record only to be confounded by not being able to specify the direction for the elements of the record? In this article we will explore how to do this with either VHDL-2019 interfaces or OSVVM interfaces. VHDL-2019 Interfaces Step 1: A Record is the foundation VHDL-2019 interfaces start with a recor... »
VHDL-2019: the Users Standard
VHDL-2019 was approved by IEEE RevCom in September 2019 and published in December 2019. It was an effort supported mainly by VHDL users – from requirements definition to LRM writing. This is different from the past where employees of EDA vendors did much of the work – particularly the LRM writing. Language changes were use model driven and had multiple opportunities to be pruned from implementatio... »
Announcing OSVVM 2020.05
Up your verification game with the latest from Open Source VHDL Verification Methodology (OSVVM). OSVVM simplifies your FPGA and ASIC verification tasks by providing utility and model libraries. Using these free, open source libraries you can create a simple, powerful, concise, and readable testbench that is suitable for either a simple FPGA block or a complex ASIC. According to the 2018 Wilson Ve... »
VHDL and OSVVM On-Line Training
Ready to go the next step with OSVVM? OSVVM training is available on-line and on-site. Our on-line classes are live sessions with OSVVM author, Jim Lewis. Through SynthWorks, Mr Lewis has been offering VHDL training for 25+ years and on-line training for 10+ years. So don’t worry, we got this. Your on-line class session will be great. Our on-line class sessions are offered in a relax... »
OSVVM at OSDA and ESA’s SEFUW
I will be in Europe in March doing presentations on Open Source VHDL Verification Methodology (OSVVM) at the 2nd Workshop on Open-Source Design Automation (OSDA) and at the 5th Space FPGA Users Workshop (SEFUW). OSDA, Friday March 13 First stop is Grenoble, France. I will be presenting an hour long talk on OSVVM on Friday March 13 at OSDA which is held in conjunction with Design, Automation, an... »
OSVVM.org is back!
Over the last year, OSVVM has been growing rapidly. I was delighted to have the opportunity to present OSVVM papers at FPGA World (both Stockholm and Copenhagen) and at DVCon Europe in Munich. In addition, between September and November 2019, I delivered six (!) OSVVM focused Advanced VHDL Testbench and Verification training courses through my company SynthWorks and through our European partners F... »
OSVVM, The #1 VHDL Verification Library
Open Source VHDL Verification Methodology (OSVVM) has been named the number #1 VHDL Verification Library by The 2018 Wilson Research Group ASIC and FPGA Functional Verification Study. While your EDA vendor may have told you that only enthusiasts use VHDL for verification, the survey results report that OSVVM is used as the FPGA Verification Library for 17% of world wide market. According to the s... »
OSVVM gone Apache … on the path to IEEE Open Source
In the latest release of Open Source VHDL Verification Methodology (OSVVM), all licenses for the entire OSVVM library (utility and model libraries) were updated to Apache 2.0 license. This is being done in preparation to migrate OSVVM to IEEE Open Source. VHDL’s adventure started with IEEE Open Source started with a pilot program for releasing the IEEE std 1076-2019 (VHDL LRM) pac... »
Webinar: Creating an AXI4 Lite, Transaction Based VHDL Testbench with OSVVM
Open Source VHDL Verification Methodology (OSVVM) simplifies your FPGA and ASIC verification tasks by providing utility and model libraries. Using these free, open source libraries you can create a simple, powerful, concise, and readable testbench that is suitable for either a simple FPGA block or a complex ASIC. This webinar is a guided walk-through of the OSVVM verification framework and transac... »