INTRODUCTION Most people don’t think of VHDL as a verification language. However, with the Open Source VHDL Verification Methodology (OSVVM) utility and verification component libraries it is. Using OSVVM we can create readable, powerful, and concise VHDL verification environments (testbenches) whose capabilities are similar to other verification languages, such as SystemVerilog and UVM. Thi... »
Up your VHDL verification game with the latest from Open Source VHDL Verification Methodology (OSVVM). OSVVM 2020.07 focuses on Verification Components. AXI4 Full models were added. Axi4Lite, AxiStream, and UART models were updated to use the new OSVVM Model Independent Transactions. AXI4 (and Axi4Lite) verification components are the most challenging and most interesting I have worked on. O... »
Ever wanted to encapsulate all the signals of an interface (such as AXI4Lite, I2C, …) into a single record only to be confounded by not being able to specify the direction for the elements of the record? In this article we will explore how to do this with either VHDL-2019 interfaces or OSVVM interfaces. VHDL-2019 Interfaces Step 1: A Record is the foundation VHDL-2019 interfaces start with a recor... »
VHDL-2019 was approved by IEEE RevCom in September 2019 and published in December 2019. It was an effort supported mainly by VHDL users – from requirements definition to LRM writing. This is different from the past where employees of EDA vendors did much of the work – particularly the LRM writing. Language changes were use model driven and had multiple opportunities to be pruned from implementatio... »
Up your verification game with the latest from Open Source VHDL Verification Methodology (OSVVM). OSVVM simplifies your FPGA and ASIC verification tasks by providing utility and model libraries. Using these free, open source libraries you can create a simple, powerful, concise, and readable testbench that is suitable for either a simple FPGA block or a complex ASIC. According to the 2018 Wilson Ve... »
Ready to go the next step with OSVVM? OSVVM training is available on-line. Our on-line classes are live sessions with OSVVM author, Jim Lewis. Through SynthWorks, Mr Lewis has been offering VHDL training for 20+ years and on-line training for 7+ years. So don’t worry, we go this. Your on-line class session will be great. Our on-line class sessions are offered in a relaxing “hal... »
I will be in Europe in March doing presentations on Open Source VHDL Verification Methodology (OSVVM) at the 2nd Workshop on Open-Source Design Automation (OSDA) and at the 5th Space FPGA Users Workshop (SEFUW). OSDA, Friday March 13 First stop is Grenoble, France. I will be presenting an hour long talk on OSVVM on Friday March 13 at OSDA which is held in conjunction with Design, Automation, an... »
Over the last year, OSVVM has been growing rapidly. I was delighted to have the opportunity to present OSVVM papers at FPGA World (both Stockholm and Copenhagen) and at DVCon Europe in Munich. In addition, between September and November 2019, I delivered six (!) OSVVM focused Advanced VHDL Testbench and Verification training courses through my company SynthWorks and through our European partners F... »
Open Source VHDL Verification Methodology (OSVVM) has been named the number #1 VHDL Verification Library by The 2018 Wilson Research Group ASIC and FPGA Functional Verification Study. While your EDA vendor may have told you that only enthusiasts use VHDL for verification, the survey results report that OSVVM is used as the FPGA Verification Library for 17% of world wide market. According to the s... »