Hi, My name is Timothy Stotts, an FPGA and Embedded Systems engineer in upstate New York. There is an often less-discussed technique of adding vendor models to the VHDL test-bench for verifying the peripheral driver and functional behavior of your FPGA design. A quick search on Google shows little documentation on adding IC vendor models to a VHDL test-bench. And during my work experience, the top... »
There is still space available in the next OSVVM Bootcamp: Advanced VHDL Testbenches and Verification class. Up level your VHDL verification skills. In Europe, Enroll with FirstEDA at: https://firsteda.com/online-vhdl-training In US + Other Locations, enroll with SynthWorks at: https://synthworks.com/public_vhdl_courses.htm »
OSVVM’s 2020.12 release introduces Virtual Transaction Interfaces (VTIs). VTIs allow us to connect to verification components (VCs) without using any ports or signals in the testbench framework. This capability is important when the verification component is embedded in the design – such as an embedded processor like ZYNQ. In this situation, we want to avoid adding “testben... »
2020 was quite a year. While everything else was quite dark, OSVVM had a great 2020. Normally I travel for work around 75K air miles. 2020 none. This saved a lot of time. All of that time (and more) went into enhancing OSVVM. OSVVM had 6 updates in 2020. This includes the 2020.12 revision which was released late on December 31. More on 2020.12 in a future post. Here are some milestones t... »
VHDL-93 (IEEE 1076-1993) created shared variables of an ordinary type as a temporary solution – which was noted in the standard document (aka LRM). VHDL-2000 (IEEE 1076-2000) created protected types as the only type to be used with shared variables and deprecated and removed the usage of a shared variable with an ordinary type. One of the places shared variables of an ordinary type are still use... »
Verification components have become an essential part of a structured VHDL environment. In OSVVM we implement verification components as an entity and architecture. This provides RTL engineers with a familiar environment to create model behavior. The objective of any verification framework is to make the Device Under Test (DUT) “feel like” it has been plugged into the board. Henc... »
The OSVVM 2020.10 release is finally out. Why 2020.10? Yes I realize it is now late November. So why 2020.10? In late October, the code was done and marked as 2020.10 with the expectation that the documentation would be done before the end of the month. The documentation took much longer than I expected and a few other items intervened. Rather than take more time and re-mark the code as 2020.11, i... »
OSVVM Model Independent Transactions I take great joy in reuse – this is true whether it is a plastic bag or VHDL code. OSVVM Model Independent Transactions were added in the 2020.07 release and are directed at improving reuse – and hence bring me great joy. Model Independent Transactions provide two aspects of reuse. First, they simplify verification component development by reducing the number... »
It has been a busy summer for OSVVM. With the world working out of home offices, all of our training has shifted to on-line – which fortunately we started doing 7+ years ago. Not having to travel has freed up additional time that I have devoted to OSVVM development. Updates started with adding PASSED counts to the AlertLog data structure in 2020.05. AXI Full verification components (ma... »
INTRODUCTION Most people don’t think of VHDL as a verification language. However, with the Open Source VHDL Verification Methodology (OSVVM) utility and verification component libraries it is. Using OSVVM we can create readable, powerful, and concise VHDL verification environments (testbenches) whose capabilities are similar to other verification languages, such as SystemVerilog and UVM. Thi... »