Hassan
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Hassan started the topic Optional ports on AXI stream transmitter and receiver cannot be left unused in the forum OSVVM 6 months, 1 week ago
I have used the AXI stream testbench to create my own for my design. The thing is, I do not need to use all the optional signals that are part of the AXI Stream interface. I am only using these on my DUT: valid, enable, data, user. I am not using these on my DUT: TID, TDest, TUser, TStrb, TKeep, TLast.
For the unused AXI stream signals on my DUT…[Read more]
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Hassan replied to the topic VHDL Assert that prints the entity instance name and path in the forum VHDL 6 months, 2 weeks ago
I have used these 3 attributes in a process but it seems that Quartus synthesis does not support any of them at all. It just gives error “predefined attribute … is not supported”
p_assert_generics: process
beginreport p_assert_generics’simple_name severity warning;
report p_assert_generics’instance_name severity warning;…[Read more] -
Hassan started the topic VHDL Assert that prints the entity instance name and path in the forum VHDL 6 months, 2 weeks ago
This question is specifically about Assert used to validate the generics of VHDL entity. It is clear that one can use Assert statement to check the value of generic and if the assert fails, the synthesis will stop with error.
There are two basic questions about this:
1. Should such an Assert statement be inside or outside process? Different…[Read more]
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Hassan replied to the topic Dissecting the OSVVM AXI Master BFM in the forum OSVVM 6 months, 3 weeks ago
I can see that the scripts use the explicit name of the file for analyze and run_test TCL commands. However, it is also possible to just do a file search and with the filenames in a list, iterate over the list and call analyze or run_test for each of them.
Why isn’t it done in this way?
Also, I was expecting to see a whole lot of commands that…[Read more]
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Hassan replied to the topic Running AXI4 Simulation from OSVVM Libraries repository in the forum OSVVM 6 months, 3 weeks ago
When OSVVM is compiling files, I get a whole lot of messages like this:
# QuestaSim-64 vcom 10.6c Compiler 2017.07 Jul 26 2017
# Start time: 23:57:14 on Jun 06,2024
# vcom -2008 -work osvvm_cosim ../OsvvmLibraries/CoSim/src/CoSimInterruptHandler.vhd
# — Loading package STANDARD
# — Loading package TEXTIO
# — Loading package std_logic_1164
# –…[Read more] -
Hassan replied to the topic Dissecting the OSVVM AXI Master BFM in the forum OSVVM 6 months, 3 weeks ago
The functions that are used to perform interface transactions and directive transactions are quite flexible and numerous. They include blocking and non-blocking calls aka asynchronous. These applies to the manager and subordinate, both read and write and also check functions.
Why is there need to have both blocking and non-blocking function…[Read more]
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Hassan replied to the topic Dissecting the OSVVM AXI Master BFM in the forum OSVVM 6 months, 3 weeks ago
The MIT document for streaming and address mapped interfaces states this: “One of the challenges of using a single record, such as AddressBusRecType, as an interface is dealing with multiple drivers on each record element. OSVVM does this giving each element a resolved type, such as bit_max, std_logic_vector_max_c, integer_max, time_max, and…[Read more]
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Hassan replied to the topic Check functions in OSVVM in the forum OSVVM 6 months, 3 weeks ago
The scoreboards can contain tags for “out of order” transactions and can also drop transactions. This makes them more sophisticated then mere FIFOs. But what more features could they be given when you say “There is a long term plan to give users more direct control of the output of scoreboards.”
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Hassan replied to the topic Dissecting the OSVVM AXI Master BFM in the forum OSVVM 6 months, 3 weeks ago
This code confused me and is found in the AXI4 manager source:
— Initialize DelayCoverage Models
AddBins (WriteAddressDelayCov.BurstLengthCov, GenBin(2,10,1)) ;
AddBins (WriteAddressDelayCov.BeatDelayCov, GenBin(0)) ;
AddBins (WriteAddressDelayCov.BurstDelayCov, GenBin(2,5,1)) ;…
— Valid Delay between…[Read more]
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Hassan replied to the topic Log, Alert and Affirm in OSVVM in the forum OSVVM 6 months, 3 weeks ago
That means normally we would not need to use Alert, but only the Affirm functions?
By the way, I did attend your course on OSVVM many years ago, before COVID. I was quite unwell in that week when I attended and could not absord the finer points. I had one more colleague with me. That colleague left a few wekks later and a redundancy drive a few…[Read more]
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Hassan started the topic Check functions in OSVVM in the forum OSVVM 6 months, 4 weeks ago
When looking at the VC documentation and related code, I came across Check functions of OSVVM. Here are a few examples:
E:My_DesignsFPGAOsvvmLibrariesCommonsrcAddressBusTransactionArrayPkg.vhd (14 hits)
Line 303: procedure ReadCheck (
Line 504: procedure ReadCheckBurstVector (
Line 514: procedure ReadCheckBurstIncrement (
Line…[Read more] -
Hassan started the topic Log, Alert and Affirm in OSVVM in the forum OSVVM 6 months, 4 weeks ago
The AlertLogPkg contains three type of functions:
Log; this has following levels: ALWAYS, DEBUG, FINAL, INFO, PASSED
Alert; this has following variants: Alert, AlertIf, AlertIfNot, AlertIfEqual, AlertIfNotEqual, AlertIfDiff. THe alert has following levels: FAILURE, ERROR, WARNING.
Affirm; this has following variants: AffirmIf, AffirmIfNot,…[Read more]
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Hassan replied to the topic Running AXI4 Simulation from OSVVM Libraries repository in the forum OSVVM 6 months, 4 weeks ago
I understand that all of these are basically FIFOs. The term “scoreboard” need not confuse oneself.
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Hassan replied to the topic Dissecting the OSVVM AXI Master BFM in the forum OSVVM 6 months, 4 weeks ago
The AXI4Manager source code contains these lines in the architecture declaration part:
signal WriteAddressFifo : osvvm.ScoreboardPkg_slv.ScoreboardIDType ;
signal WriteDataFifo : osvvm.ScoreboardPkg_slv.ScoreboardIDType ;signal ReadAddressFifo : osvvm.ScoreboardPkg_slv.ScoreboardIDType ;
signal…[Read more] -
Hassan replied to the topic Dissecting the OSVVM AXI Master BFM in the forum OSVVM 6 months, 4 weeks ago
It seems that so many IDs are needed to create a hierarchical output for difference aspects of the BFM in the test result report.
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Hassan replied to the topic How to improve VHDL in the forum VHDL 6 months, 4 weeks ago
What is the primary benefit of this thread since the synthesis tool vendors will take maybe a decador or more to add simple new features for the language.
We need an effort to upgrade the flow that is used with VHDL. We need something like LLVM for VHDL. The netlist fitter can be handled by the tools. But tool for synthesis and compilation for…[Read more]
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Hassan started the topic Dissecting the OSVVM AXI Master BFM in the forum OSVVM 6 months, 4 weeks ago
This thread has been created to ask questions about the Axi4Manager found in the OSVVM AXI4 portion. This is the full AXI4 Master BFM. There is a separate BFM for the AXI4-Lite. There are two primary variants of the Axi4Manager. These are one variant without VTI (Axi4Manager) and one with VTI (Axi4ManagerVti). These only differ in how the…[Read more]
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Hassan replied to the topic Running AXI4 Simulation from OSVVM Libraries repository in the forum OSVVM 7 months ago
The AXI4Manager source code contains these lines in the architecture declaration part:
signal WriteAddressFifo : osvvm.ScoreboardPkg_slv.ScoreboardIDType ;
signal WriteDataFifo : osvvm.ScoreboardPkg_slv.ScoreboardIDType ;signal ReadAddressFifo : osvvm.ScoreboardPkg_slv.ScoreboardIDType ;
signal…[Read more] -
Hassan replied to the topic Can OSVVM Verification Component be used in VUnit based testbench? in the forum OSVVM 7 months, 1 week ago
OSVVM can generate a lot of test reports at end of a test, I believe the EndOfTestReports exists for this purpose.
Is this feature compatible with VUnit or does it require specific OSVVM scripts and script commands to be run before those design reports can be created?
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Hassan replied to the topic Running AXI4 Simulation from OSVVM Libraries repository in the forum OSVVM 7 months, 1 week ago
The TbAXI4.vhd contains AXI4 Manager and Subordinate along with the Test controller/sequencer called TestCtrl. It also contains clock and reset source.
There is one more thing called Axi4Monitor. I found a source file called Axi4Monitor_dummy.vhd which has an entity but empty architecture. Does this mean that the monitor module is not yet…[Read more]
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