fpgaphreak

Me too. What is about Jitter Simulation with min/max definitions of the phase to simulate short term jitter effects?

Although old, a late response: This topic is often discussed together with pull ups constrained in the XDC for a pin which hardly can be simulated. Together with timing demands and driver issues, which are the common problems at I2C I recommend to use an analog behaviour model which transforms both the outout of the VHDL Pin and its input to a…[Read more]

I think the complaint refers to the issue that the testbenches and example code for the design more and more is limited to Verilog for an unknown reason. Recently I again stumbled over a thing: A DDR Design cannot be built with an AXI-Interface in VHDL. The AXI is only available for Verilog.

Xilinx disreagards the fact that VHDL has certain…[Read more]

Questa Intel, yes.

So it seems more check for implementation issues rather than functional.(?)
I wonder how and in wich way one could alternatively simulation LVDS issues. Foussing on driever behavior?

Was there any reaction of Siemens? I wonder who is working there at Questa anyway – i suggest these are the former Mentor programmers?

I have the same issue here, but only newer Questa. Formerly i did not recognize this. Possibly a config issue.

My question would be what the intention is in detail: Typically sensor interfaces are simulated and tested independently from the image content. Therefore I produced a test package capeable of driving various signal schemes and bahaviour into the lvds lines which can be simulated and also synthesized into an FPGA for real investigations of eye…[Read more]

I still do not like the ambigious way, vectors are treated agains signals, and that there is conversion required in between a(0 downto 0) = “1” instead of using “a(0) = ‘1’). See the bram addressing regarding their write enable. This is one signal only, however one uses 0…0 instead of a signal. So VHDL could be made more tolerant for that.