fpgaphreak
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fpgaphreak started the topic case splitting in the forum OSVVM 6 months, 3 weeks ago
In some cases i need a full coverage of cases when doing simulations of timing critial circuits which cause deviations in behaviour. I would like to know if OSVVM supports this in any way.
To understand the issue I would like to describe the problem:
Take a signal of unknown phase and level and a synchronizer to get it into a circuit with an…[Read more]
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fpgaphreak replied to the topic Creating Asynchronous Clocks in the forum OSVVM 6 months, 3 weeks ago
Me too. What is about Jitter Simulation with min/max definitions of the phase to simulate short term jitter effects?
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fpgaphreak replied to the topic I2C Bus pins simulation? in the forum VHDL 6 months, 3 weeks ago
Although old, a late response: This topic is often discussed together with pull ups constrained in the XDC for a pin which hardly can be simulated. Together with timing demands and driver issues, which are the common problems at I2C I recommend to use an analog behaviour model which transforms both the outout of the VHDL Pin and its input to a…[Read more]
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fpgaphreak replied to the topic Xilinx not supporting VHDL anymore? in the forum VHDL 6 months, 3 weeks ago
I think the complaint refers to the issue that the testbenches and example code for the design more and more is limited to Verilog for an unknown reason. Recently I again stumbled over a thing: A DDR Design cannot be built with an AXI-Interface in VHDL. The AXI is only available for Verilog.
Xilinx disreagards the fact that VHDL has certain…[Read more]
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fpgaphreak replied to the topic Questa-Intel & Reports in the forum OSVVM 6 months, 3 weeks ago
Questa Intel, yes.
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fpgaphreak replied to the topic Custom VC for image-sensor interface in the forum OSVVM 1 year, 9 months ago
So it seems more check for implementation issues rather than functional.(?)
I wonder how and in wich way one could alternatively simulation LVDS issues. Foussing on driever behavior? -
fpgaphreak replied to the topic Questasim Version in the forum OSVVM 1 year, 9 months ago
Was there any reaction of Siemens? I wonder who is working there at Questa anyway – i suggest these are the former Mentor programmers?
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fpgaphreak replied to the topic Questa-Intel & Reports in the forum OSVVM 1 year, 9 months ago
I have the same issue here, but only newer Questa. Formerly i did not recognize this. Possibly a config issue.
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fpgaphreak replied to the topic Custom VC for image-sensor interface in the forum OSVVM 1 year, 9 months ago
My question would be what the intention is in detail: Typically sensor interfaces are simulated and tested independently from the image content. Therefore I produced a test package capeable of driving various signal schemes and bahaviour into the lvds lines which can be simulated and also synthesized into an FPGA for real investigations of eye…[Read more]
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fpgaphreak replied to the topic How to improve VHDL in the forum VHDL 1 year, 9 months ago
I still do not like the ambigious way, vectors are treated agains signals, and that there is conversion required in between a(0 downto 0) = “1” instead of using “a(0) = ‘1’). See the bram addressing regarding their write enable. This is one signal only, however one uses 0…0 instead of a signal. So VHDL could be made more tolerant for that.
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fpgaphreak's profile was updated 1 year, 9 months ago
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fpgaphreak changed their profile picture 1 year, 9 months ago
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fpgaphreak became a registered member 1 year, 10 months ago