Activity
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Martin became a registered member 5 years, 11 months ago
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Jim Lewis wrote a new post 5 years, 11 months ago
Over the last year, OSVVM has been growing rapidly. I was delighted to have the opportunity to present OSVVM papers at FPGA World (both Stockholm and Copenhagen) and at DVCon Europe in Munich. In addition, between […]
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Evert Scholtz's profile was updated 5 years, 11 months ago
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Maksim's profile was updated 5 years, 11 months ago
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Qing became a registered member 5 years, 11 months ago
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Ian Gibbins wrote a new post 5 years, 11 months ago
Open Source VHDL Verification Methodology (OSVVM) has been named the number #1 VHDL Verification Library by The 2018 Wilson Research Group ASIC and FPGA Functional Verification Study.
While your EDA vendor may […]

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Ian Gibbins wrote a new post 5 years, 11 months ago
In the latest release of Open Source VHDL Verification Methodology (OSVVM), all licenses for the entire OSVVM library (utility and model libraries) were updated to Apache 2.0 license. This is being done in p […]
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Jim Lewis wrote a new post 5 years, 11 months ago
Open Source VHDL Verification Methodology (OSVVM) simplifies your FPGA and ASIC verification tasks by providing utility and model libraries. Using these free, open source libraries you can create a simple, […]

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I was wondering, if the webinar is recorded – and if yes, how to access it – for the OSVVM enthusiast, who unfortunately missed the event?
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Hi Cahit,
Yes it will be posted shortly at Aldec (the good folks who hosted the webinar).Best Regards,
Jim-
Looking forward to it 🙂
Thanks Jim.
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Hi Cahit,
Here is the link to the recorded webinar. To get to it, you need to register with Aldec (who hosted the webinar).
https://www.aldec.com/en/support/resources/multimedia/webinars/2083Best Regards,
Jim
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Feda Demo became a registered member 6 years ago
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Sebastian Zanker replied to the topic OSVVM and Cadence Simulator in the forum OSVVM 7 years, 4 months ago
Hi Jim,I mailed the log files to your Synthworks Mail.Kind regardsSebastian
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Jim Lewis replied to the topic Coverage and sequences in the forum OSVVM 7 years, 5 months ago
Sure, it is easy. Sequences imply history. We create history explicitly just like RTL – by using clocked processes / flip-flops. Once you have history, this is just a simple cross product of selected current values and two previous values. WRT sampling, in OSVVM, we trigger on transaction completion using an explicit call to…
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Barry Henderson replied to the topic failure to compile a Scoreboard in Modelsim DE using osvvm 2018.04 in the forum OSVVM 7 years, 5 months ago
Hi Jim, Many thanks for your answer. My problem is that i have tried every which way to get things to compile and i always get errors.My scoreboard generic package is defined like this now in a seperate design unit (i.e. a VHDL file):library IEEE;use IEEE.STD_LOGIC_1164.ALL;library osvvm;–use osvvm.OsvvmContext;use OSVVM.ScoreboardGenericPkg;use…[Read more]
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Jim Lewis replied to the topic Comparing Two std_logic_vectors in the forum VHDL 7 years, 5 months ago
Hi Torsten,In the IEEE VHDL-2008, there is only numeric_std_unsigned. There is no “signed” package. Jim
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Jorge Tonfat replied to the topic Correct usage of WriteCovDb and ReadCovDb in the forum OSVVM 7 years, 6 months ago
Hi Jim,I found in the ALDEC documentation how to merge the functional coverage using the acdb edit command.Example:
## Merge functional coverage from TSSPWIPacdb edit -i "$dsn/src/Unit Test/unittest.acdb" -move -merge instance /unittest/TSSPWIP/TC* /unittest/TSSPWIP/TC3RecvErrBest regards,Jorge -
Jim Lewis wrote a new post 7 years, 9 months ago
Webinar Taming Testbench Messaging and Error Reporting with OSVVM’s Logs and Alerts.
Thursday April 5, 2018
Printing and error reporting in VHDL are tedious, yet necessary testbench tasks. Fortunately, Open S […] -
Torsten replied to the topic Random seed problem in the forum OSVVM 7 years, 12 months ago
Thanks, I get far better results with your workaround. If we change the seed function, we could look what kind of hash functions are used for dictionary types in languages like python. I assume, they use functions which are not cryptographic secure, but have a good uniform distribution and are very fast. But you are right, with such a change, the…[Read more]
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Jim Lewis replied to the topic Possible bug in AlertLogPkg's Log procedure. in the forum OSVVM 8 years ago
Hi Reuven,PathTail is intended to extract a component instance label from a PathName. For the string representation of a variable, signal, constant, or even entity name, you can indeed just use simple_name. I will update PathTail in the next revision so that it does not assume the name ends in a “:” and will return what you were…[Read more]
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Tim Wells replied to the topic Positive Acknowledge in Alerts in the forum OSVVM 8 years ago
Hi Jim,I would like positive acknowledge in the Report Status. My end client is doing DO-254 with OSVVM and my company is struggling to integrate the two.Thanks,Tim
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Jim Lewis wrote a new post 8 years, 3 months ago
OSVVM: TrainingOSVVM Training Dates Advanced VHDL Testbenches and Verification – OSVVM+ Boot Camp Like the Webinar? Ready to make Open Source VHDL Verification M […]
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Jim Lewis replied to the topic Cannot compile the library with Modelsim 10.5b in the forum OSVVM 8 years, 4 months ago
I test with QuestaSim 10.5b so if you have the compile order correct, you should be fine.How did you compile it? Did you use the osvvm.do file? See: https://github.com/OSVVM/OSVVM/blob/master/osvvm.doDid you use the directions in the OSVVM_release_notes.pdf? See: https://github.com/OSVVM/OSVVM/blob/master/doc/osvvm_release_notes.pdfI note…[Read more]
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