OS-VVM in general
Announcing OSVVM Release 2014.01
OSVVM release 2014.01 is now available at OSVVM Downloads. Note that starting with this release, I have separated the examples from the release of the library. Message handling is now handled by separate package, MessagePkg. MessagePkg must be compiled before CoveragePkg. Suggested compile order: MessagePkg.vhd SortListPkg_int.vhd RandomBasePkg.vhd RandomPkg.vhd CoveragePkg.vhd What’s new in... »
OSVVM World Tour
In conjunction with FirstEDA, I taught the first two European sessions of our OSVVM and Transaction Level Modeling (TLM) focused Advanced VHDL Testbenches and Verification class. We had attendees from many of the major European System Companies who design and verify programmable devices (FPGAs). The skill level of the delegates was impressive and made teaching one of my favorite classes just that ... »
VHDL Functional Coverage is more capable than SystemVerilog
When writing functional coverage it is important to be able to capture all the details of a model. With item (aka point) coverage, both VHDL and SystemVerilog do a good job. However with cross coverage, if the model requires more than a simple Cartesian product, SystemVerilog falls short. OSVVM, on the other hand, offers a rich cross coverage capability. Post continues at SynthWorks OSVVM Blog »