OS-VVM in general
Why no constraint solver? Are you going to add one?
Nope. No constraint solver. Instead OS-VVM implements an innovative “Intelligent Testbench” feature that does a random walk across functional coverage holes. We call this feature “Intelligent Coverage”. Constraint solvers are yesterday’s verification technology. Intelligent testbenches are the way forward. In his 2011 DVCON address, Mentor Graphics CEO Wally Rhines noted that constrained rand... »
OS-VVM Updates
Hello Fellow OS-VVMers, Thanks to everybody who attended our DAC2012 meeting and provided feedback — first results are visible in the revision 2.3.1 of OS-VVM package posted today in the Downloads section. Here are the highlights: Minor updates to package sources. Simplified version of SENSORS example (should work consistently on all simulation platforms, but requires coverage package from t... »
Let’s Meet At DAC…
Semi-formal meeting of OS-VVM fans and VHDL users will be held at the 49th Digital Automation Conference (DAC 2012). The conference is located in San Francisco, California, USA this year. The entry to the exhibit hall at Moscone Center is free on Monday, June 4th – drop in if you happen to be in the area. We are meeting at the ALDEC booth (#2126) at 2pm. To help us estimate how many visitors... »