I don’t know about you, but I am tired of having to learn a new set of switches and methods to do the same tasks I already know how to do in another simulator.
What I want is one script to rule run them […]
Hi, I installed and am currently running OSVVM on my project, I have to say its been a great experience, I normally write my test benches in system verilog but we write mostly vhdl so i stumbled upon osvvm and like it alot, soo much I would like to extend the capability to synthesis. If i get it working correctly, I would like to contribute to the project if allowed to…
Contributions are welcome.
You need to do
includeuse a path reference relative to the script they are running.
Hence, in testbench.pro, it just says
analyze TestCtrl_e.vhd. The path to testbench.pro gets
automatically prepended onto the file name. Hence, when writing scripts we only need to know
As the developer of Open Source VHDL Verification Methodology (OSVVM) , I would like to invite the Universal VHDL Verification Methodology (UVVM) community to join us in using and developing OSVVM.
At this […]
In reply to a LinkedIn post that regurgitated the old statement that VHDL is verbose, I replied, “With the VHDL-2008 update, Verilog is more verbose than VHDL.”
This led my old friend Cliff Cummings and I to […]
VHDL + Open Source VHDL Verification Methodology (OSVVM) is great for verification and is a competitor to SystemVerilog + UVM. Especially in the FPGA space where VHDL is the dominant language (see the 2020 […]
A quick update. I am working with Cadence on Xcelium. Things are looking up. I should have more news on this shortly.
I have provided them with the full OSVVM regression suite. I am optimistic, but I don’t know the time frame for them to update Xcelium.
A quick update. I am working with Synopsys on VCS. Things are looking up. I should have more news on this shortly.
Apparently the mcode version of GHDL errors out if you subtract 1 from an uninitialized integer.
All other simulators are ok with this. OTOH, it was easy enough to fix. So there is
now a fix in the 2021.07 release. It is on GitHub now. It will be on OSVVM.org
Are you running Ubuntu with the GCC build? Try either the mcode or lvvm. Unai setup CI for OSVVM. Prior to this I was testing OSVVM only on Windows 10 with 64 bit llvm. In testing we found that Ubuntu with GCC is not working for some items. I have not looked at the bugs, however, since it works for Ubuntu with mcode and lvvm and widows…[Read more]
WRT OSVVM and xsim/Vivado. Here is the current update (July 2021):
I compiled all files on 2021.1. That was momentary good news. However, some packages do not work yet in simulation. In particular, AlertLogPkg. It needs a deep dive into root cause like I did for the AXI verification components in GHDL. It worked well in GHDL since I could find one…[Read more]
I should also note that the Virtual Transaction Interfaces (VC with suffix of Vti) use external names and GHDL does not support external names.
This is currently what I am running in the OSVVM libraries for regression:
# Run Tests
# Next one has failures in running tests
I am running GHDL version: GHDL 2.0.0-dev (1.0.0.r292.g3807826b) [Dunoon edition]
This is from one of the nightly builds. All of 2021.06 compiles. All of 2021.06 simulates except Axi4Lite – Axi4 Full was updated to work with GHDL – so you can use that instead. The Axi4Lite updates will be coming later this year.
In this second webinar of the VHDL-2019: Just the New Stuff series we will focus on enhancements to VHDL’s protected type capabilities.
Protected types simplify and abstract the construction of data […]
IEEE 1076-2019, fondly referred to as VHDL-2019, was approved by IEEE RevCom in September 2019 and published in December 2019. The effort was supported mainly by VHDL users – from requirements definition to L […]
Up your verification game with the latest from Open Source VHDL Verification Methodology (OSVVM).
OSVVM simplifies your FPGA and ASIC verification tasks by providing utility and model libraries. Using these […]
My name is Timothy Stotts, an FPGA and Embedded Systems engineer in upstate New York. There is an often less-discussed technique of adding vendor models to the VHDL test-bench for verifying the peripheral […]
There is still space available in the next OSVVM Bootcamp: Advanced VHDL Testbenches and Verification class. Up level your VHDL verification skills.
In Europe, Enroll with FirstEDA at: […]
OSVVM’s 2020.12 release introduces Virtual Transaction Interfaces (VTIs). VTIs allow us to connect to verification components (VCs) without using any ports or signals in the testbench framework. This cap […]
Testing for OSVVM 2020.12 release was done on RivieraPro 2020.10 and ModelSim 2020.01. Unfortunately I did not test with QuestaSim 2020.04 (my licenses are for a machine that I just finished setting up today).
There appears to be a subtle bug in QuestaSim that causes a SEGV Fatal when doing Burst Transfers (such as TbAxi4_MemoryBurst1). I…[Read more]
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