Jim Lewis
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Jim Lewis replied to the topic OSVVM 2020.08 New user experience in the forum OSVVM 4 years ago
#1 I use “run all” to run my tests. std.env.stop will stop the test. However, stop works much like a breakpoint, so the simulation can be continued. I am ok with this.
If you wanted to prohibit the testbench from running further after it stops, use std.env.finish instead. It also allows an integer parameter, so you can call it…[Read more]
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Jim Lewis replied to the topic OSVVM 2020.08 New user experience in the forum OSVVM 4 years ago
Hi Chengshan,
>1. Could the test bench be stopped gracefully by stopping all clocks?
Do you have a method to gracefully stop clocks? Everything I have seen
has overhead incurred at least once per clock cycle (or some multiple of
the clock cycle).OTOH, I really like std.env.stop. It only incurs overhead when
it is actually stopping the…[Read more] -
Jim Lewis replied to the topic OSVVM 2020.08 New user experience in the forum OSVVM 4 years ago
Hi Chengshan,
3. Correct. The 2020.08 Axi4Responder_Transactor.vhd is intended to be a register access model and does not support bursting. As you noted, Axi4Memory.vhd, implements memory models and does support bursting. This is noted in the README.md at: https://github.com/osvvm/AXI4.
Do you need a transactor that supports bursting? It…[Read more]
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Jim Lewis replied to the topic OSVVM 2020.08 New user experience in the forum OSVVM 4 years ago
Hi Chengshan,
2. The test sequencer interface to AXI verification component burst FIFO is 8 bits. The AXI verification component assembling this into the size of the data bus. So you will always push bytes into the FIFO – even if you make the data bus bigger or smaller. It was tested with a 32 bit AXI data bus, however, it is intended to…[Read more]
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Jim Lewis replied to the topic OSVVM 2020.08 New user experience in the forum OSVVM 4 years ago
Hi Chengshan,
4. Typo! You are correct, AxRegion should be 4 bits. I will fix that
in the next release. Anything else like that is an issue?What do you mean you had to change the width to make it compile? Is this to
connect it to your design? It compiles and runs fine with the OSVVM models
which all use the same incorrectly sized…[Read more] -
Jim Lewis replied to the topic OSVVM 2020.08 New user experience in the forum OSVVM 4 years ago
Hi Chengshan,
First, thanks for the feedback.Are you using this with a particular design?
You have four questions, so I will give 4 separate answers.
Best Regards,
Jim -
Jim Lewis wrote a new post 4 years ago
OSVVM Model Independent Transactions
I take great joy in reuse – this is true whether it is a plastic bag or VHDL code. OSVVM Model Independent Transactions were added in the 2020.07 release and are di […] -
Jim Lewis wrote a new post 4 years ago
It has been a busy summer for OSVVM. With the world working out of home offices, all of our training has shifted to on-line – which fortunately we started doing 7+ years ago. Not having to travel has freed up […]
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Jim Lewis wrote a new post 4 years ago
INTRODUCTION
Most people don’t think of VHDL as a verification language. However, with the Open Source VHDL Verification Methodology (OSVVM) utility and verification component libraries it is. Using OSVVM we can […] -
Jim Lewis wrote a new post 4 years, 1 month ago
Up your VHDL verification game with the latest from Open Source VHDL Verification Methodology (OSVVM).
OSVVM 2020.07 focuses on Verification Components. AXI4 Full models were added. Axi4Lite, Axi […]
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Jim Lewis wrote a new post 4 years, 1 month ago
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Jim Lewis wrote a new post 4 years, 2 months ago
Ever wanted to encapsulate all the signals of an interface (such as AXI4Lite, I2C, …) into a single record only to be confounded by not being able to specify the direction for the elements of the record?
In t […]
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Jim Lewis wrote a new post 4 years, 3 months ago
VHDL-2019 was approved by IEEE RevCom in September 2019 and published in December 2019. It was an effort supported mainly by VHDL users – from requirements definition to LRM writing. This is different from t […]
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Jim Lewis wrote a new post 4 years, 4 months ago
Up your verification game with the latest from Open Source VHDL Verification Methodology (OSVVM).
OSVVM simplifies your FPGA and ASIC verification tasks by providing utility and model libraries. Using these […]
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Jim Lewis replied to the topic UCIS / UCDB in the forum OSVVM 4 years, 4 months ago
Hi Michael,
Stefan Bauer out of the Mentor German office says he has written one. Last I knew, it is only available by request. I have made another inquiry about it.Best Regards,
Jim -
Jim Lewis replied to the topic Question to the OSVVM community: how to approach the methodology, learning curve in the forum OSVVM 4 years, 5 months ago
To answer your questions:
1. How much time is needed?
In an instructor led class, you can learn OSVVM is 5 days. With our on-line classes, this translates to 10 on-line sessions – each session is approximately 2.5 hours of lecture (currently done via GoToMeeting) and 2.5 hours of lab (done on your own with support via email, phone, and…[Read more] -
Jim Lewis wrote a new post 4 years, 5 months ago
Ready to go the next step with OSVVM? OSVVM training is available on-line.
Our on-line classes are live sessions with OSVVM author, Jim Lewis. Through SynthWorks, Mr Lewis has been offering VHDL tra […]
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Jim Lewis commented on the post, Webinar: Creating an AXI4 Lite, Transaction Based VHDL Testbench with OSVVM 4 years, 6 months ago
Hi Cahit,
Here is the link to the recorded webinar. To get to it, you need to register with Aldec (who hosted the webinar).
https://www.aldec.com/en/support/resources/multimedia/webinars/2083Best Regards,
Jim -
Jim Lewis wrote a new post 4 years, 6 months ago
I will be in Europe in March doing presentations on Open Source VHDL Verification Methodology (OSVVM) at the 2nd Workshop on Open-Source Design Automation (OSDA) and at the 5th Space FPGA Users Workshop […]
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Jim Lewis replied to the topic Intelligent Coverage Random test generation in the forum OSVVM 4 years, 7 months ago
Hi Ken,
Yes and no. SV does not have this built into it or the UVM library.OTOH, Accellera created a language that layers on top of other languages (I think VHDL too), called PSS (Portable Test and Stimulus Standard). Of course, it adds another layer of $$$$$ to your simulator budget.
Best Regards,
Jim - Load More