Activity – Jim Lewis – Open Source VHDL Verification Methodology

Jim Lewis wrote a new post 1 year, 7 months ago

OSVVM 2023.01 Release Summary of 2023.01 Changes Co-simulation environment that supports running software (C++) in a hardware simulation environment. Added […]
Jim Lewis wrote a new post 1 year, 9 months ago

Summary of 2022.12 Changes

Updated StartUp.tcl to use OSVVM_TOOL environment variable to determine which tool is run when none is found
Updated scripts for Synopsys VCS and Cadence Xcelium […]
Jim Lewis replied to the topic Questa-Intel & Reports in the forum OSVVM 1 year, 9 months ago

Is that the Questa Intel edition or another edition?
Jim Lewis replied to the topic Expected alerts generation in the forum OSVVM 1 year, 9 months ago

Hi Anna,
Two thoughts on that.

First, there is no need for an expected SLVERR to be an actual test case error. The following is from p37 of the Axi4_VC_user_guide.pdf that is in the documentation repository:

By default, the expected value for BRESP and RRESP are OKAY. When testing a subordinates response to an incorrect address, a SLVERR is…[Read more]
Jim Lewis replied to the topic Verification with SystemVerilog or VHDL in the forum OSVVM 1 year, 9 months ago

Hi Oliver,
There is an OSVVM SPI model at: https://github.com/noasic/SPI

My long term plan is to clone it. It is a candidate for inclusion in OSVVM.

Best Regards,
Jim
Jim Lewis replied to the topic Synopsys VCS-MX in the forum OSVVM 1 year, 9 months ago

Hi Antonio,
I did some testing with Synopsys over the last week.

It looks like when I added the error handling to the scripts, it broke the scripts for Synopsys. Unfortunately at the time I added the error handling to other aspects of the scripts, I did not have active Synopsys licenses.

I have updated the scripts now and they are working…[Read more]
Jim Lewis replied to the topic Include If Statement For Scripting Process in the forum OSVVM 1 year, 9 months ago

Hi Michael,
Sorry I missed your post.

OSVVM pro scripts are a abstract procedure layer on top of TCL. Hence, you can do anything that TCL does. See the scripts OsvvmLibraries/OsvvmLibraries.pro and OsvvmLibraries/osvvm/osvvm.pro for examples.

Best Regards,
Jim
Jim Lewis replied to the topic OSVVM and Cadence Xcelium in the forum OSVVM 1 year, 9 months ago

Hi Steve,
I did some testing with Cadence over the last week. Looks like the 2022.08 updates to memory pkg broke some things. On the dev branch of OSVVM, I moved MemoryPkg_c.vhd back to the 2022.06 version.

It also looks like Cadence is failing the singleton tests in CoveragePkg. I need to try to find root cause as the singleton tests in…[Read more]
Jim Lewis replied to the topic Verification with SystemVerilog or VHDL in the forum OSVVM 1 year, 9 months ago

Hi Oliver,
> Above all, there is no SystemVHDL as a complement to the SystemVerilog
Renaming Verilog to SystemVerilog is simply marketing. Just asking that question demonstrates the brilliance it.

OSVVM provides VHDL with “SystemVerilog + UVM” verification capabilities including Transaction Level Modeling, Constrained Random, Functional…[Read more]
Jim Lewis replied to the topic Custom VC for image-sensor interface in the forum OSVVM 1 year, 9 months ago

Hi Thomas,
I try to divide the concerns into what must be done for every transaction and what is stable for a long period of time. Things that are stable for a long period of time can be set with SetModelOptions.

The error injection probability is a candidate for SetModelOptions.

You may wish for things like Image Width, Height, Color Depth,…[Read more]
Jim Lewis wrote a new post 1 year, 9 months ago

As I was writing the blog about the 2022.10 Multiple Verification Component example, my focus was drawn to the issue, “How do I call transactions that iterate across an array of verification components?” […]
Jim Lewis replied to the topic Memory leak or not ? in the forum VHDL 1 year, 10 months ago

Memory leak. I do not think the simulators are able to handle this for you.

I should note general VHDL questions like this may get a response faster on StackOverflow, however, I have indeed encountered this one and know a couple of solutions.

The simplest that I have seen, but not used (so it may have flaws) is:

`vhdl
function my_function(obj…[Read more]
Jim Lewis replied to the topic Passing arguments to simulation run script in the forum OSVVM 1 year, 10 months ago

Hi Anna,
Sorry, some how while answering your questions on GitHub, I missed your question here.

For all others, here is a summary of the resolution of Anna’s question.

With the 2022.10 update, the same actions can be accomplished with the following call to simulate. Note while the items in square brackets are optional, if you use generic…[Read more]
Jim Lewis wrote a new post 1 year, 10 months ago

Several times now I have been asked how to use multiple OSVVM VC, like a UART, in a simulation. This should be simple, however, there are a couple of VHDL and OSVVM got-yas.

For the 2022.10 release, I prepared […]
Jim Lewis wrote a new post 1 year, 10 months ago

Summary of recent changes in OSVVM.

Added Ethernet Phy and MAC verification components for GMII, RGMII, MII, RMII
Added interrupt handler that supports any verification component that uses the […]
Jim Lewis wrote a new post 1 year, 10 months ago

Don’t miss your chance to express what verification approach you use for FPGAs (OSVVM)

This is the first public survey I have seen. Others have been done by random selection and invitation only.

Survey is here
Jim Lewis wrote a new post 1 year, 10 months ago

On GitHub Issues, I had the following question, “With OSVVM scripting (.pro), is there a way to specify testbench generics, waveform files, and length of time to run a simulation.”

So lets take a look at these. […]
Jim Lewis started the topic Questa-Intel & Reports in the forum OSVVM 1 year, 11 months ago

Recently due to some issue reports, I had a look at Questa-Intel 2021.02. When I ran it, it would not create proper OSVVM log and html log messages – much of the information was missing.

The first thing I noticed is that it started up with two windows instead of just the GUI:

So I consulted with a friend of mine to see if he knew what the…[Read more]
Jim Lewis started the topic OSVVM, Questa – Fails to Compile OSVVM in the forum OSVVM 1 year, 11 months ago

In the Questa – Intel 2022.0X version, the osvvm library was removed, but the library mapping for osvvm still remains in the ini file at /questa_fse/modelsim.ini. This unfortunately prevents OSVVM from compiling.

The only way I have found to fix it is to comment out the mapping in the ini file. To do this, simply put a ‘;’ as the first…[Read more]
Jim Lewis started the topic OSVVM & Questa – Calls to PushBurstRandom in the forum OSVVM 1 year, 11 months ago

For Questa 2021.02, there is an issue with it being able to simulate calls to PushBurstRandom and CheckBurstRandom with an integer FirstWord value:
procedure PushBurstRandom ( constant Fifo : in ScoreboardIdType ; constant FirstWord : in integer ; constant Count : in integer ; constant FifoWidth : in…[Read more]
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Jim Lewis

@jiml