Jim Lewis

> 1. Do the OSVVM VC for these AMBA busses support all parts of the specification for these busses?
That is certainly the intent.

> 2. What is the difference between the OSVVM VC for these busses and the ones from UVVM?
I will only talk about the OSVVM VC as I don’t pay attention to the UVVM VC.

All OSVVM VC use the OSVVM Model Independent…[Read more]

Hi Jake,
Are you running on Linux or Windows? Currently I am testing on Windows. My contact at Siemens says there are some issues with running OSVVM in Visualizer in 2024.01. As a result, I had not put the effort into running it just yet. However I have not heard from him about 2024.03. I will check.

Best Regards,
Jim

What does your interface look like? Are there any control signals? When do you receive a result – immediately or several clocks later? What operations does it support? What is the set of values you intend to apply to your ALU to verify it?

2024.03a addresses this issue – specifically when running interactively, EndSimulation will not be called.

Hi Jeremy
Currently OSVVM is doing quit -sim when a simulation ends in error. This unfortunately is necessary to close the transcript file.

A change is coming to not do this when running interactive

Jim

Hi Mahmoud,
Please see test case OsvvmLibraries/AXI4/Axi4/TestCases/TbAxi4_ReleaseAcquireManager1.vhd

Best Regards,
Jim

For the next release of OSVVM, I have added an AlertLogID input to SafeResize and all of the OSVVM VC specify the ID on the call to SafeResize. I also updated the error message to be of the following form:

Alert ERROR in AxiManager_1, SafeResize: value changed on resize. Original value: 01AF, Resized value: AF

Hopefully this will…[Read more]

Step 1: If you have complex clock domain crossings, you probably need a clock domain crossing tool. Especially to find anything that might loop back.
Step 2: Use your directed cases to explore the relationships you understand.
Step 3: Add jitter to your clock (or clocks depending on the number of clock domains you have) so that your…[Read more]

Hi Joseph,
This is coming from the call to SafeResize that is inside of OSVVM verification components. What it is telling you is that the testbench put a value with more one’s on the left hand side of it in the call to a transaction, such as Write, Read, or Send, than is used by the verification component.

The error will happen when you call…[Read more]

Hi Jake,
Just checked the Questa command reference manual. Good catch. It is an easy fix.
In the file, VendorScripts_Siemens.tcl, all of the specialization is done. In there
the analyze for Verilog/SystemVerilog is:
`tcl
proc vendor_analyze_verilog {LibraryName FileName args} {
set AnalyzeOptions [concat [CreateVerilogLibraryParams “-l…[Read more]

Hi Jake,
This is something that one of the Siemens AEs has talked to me about and has worked on. I will have to see if he has something ready to submit for OSVVM. The plan is that Visualizer will simply use a separate VendorScripts_Visualizer.tcl. With that it should be fairly easy to do whatever visualizer needs done as all the hooks are…[Read more]

Hi Brad,
I have had on my todo list to come back to look at this example in further detail – I have just had a very busy year end for 2023.

Since I don’t have a copy of your testbench, we have only been able to talk in generalities. However, I think I see the issue in your statement here:

> When analyzing that TB file, since the generic has…[Read more]

Hi Lukas,
Do you have the output of LinkLibraryDirectory? If it is working ok, it should be something like the following:

LinkLibraryDirectory C:/tools/VHDL_LIBS/QuestaSim-2022.01
# set CurrentSimulationDirectory C:/tools/sim/questa
# vmap defaultlib C:/tools/VHDL_LIBS/QuestaSim-2022.01/defaultlib
# vmap osvvm…[Read more]

If you look at the OSVVM *.pro compile scripts you will note there are a number of places where we do not compile certain things – because of a bug in a particular tool.

Note these ports are not OPEN. Instead they have a null range, which is a valid range. Please submit a bug against Xcelium for this issue.

Hi Rishi,
The issue with 10.5b looks like a bug in that version of the tool. I don’t test with versions that old.

Best Regards,
Jim

Hi Rishi,
The issue with 2022.4 (quarter or release in 2022 not sure) / 2022.10 (10 probably is month) that says:

# ** Error: vhdl_src/std/standard.vhd: (vcom-1576) expecting IDENTIFIER or BODY.

Is a tool install issue. OSVVM does not analyze (compile) the standard package.

Best Regards,
Jim