Jim Lewis
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Jim Lewis replied to the topic Ordre of stimulus in the forum OSVVM 2 years, 3 months ago
Hi Omaima,
First, I should note you are using the older version of CoveragePkg that has a protected type interface. I suggest that you upgrade to the newer version that has a singleton interface. Please see CoveragePkg_user_guide.pdf in the OsvvmLibraries/Documentation.Coverage is a data structure. Calls are done in order and items…[Read more]
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Jim Lewis replied to the topic GENERATION OF RANDOM BYTES USING RANDOM PACKAGE ONLY in the forum OSVVM 2 years, 3 months ago
Hi Nagella
To debug your code start by reading your code out loud. Do at least 2 iterations of your process.What we see is that you are calling InitSeed before generating each value.
Why is this a problem? Verification uses pseudo random. Each seed always produces the same sequence of values. For verification pseudo random is required so your…[Read more]
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Jim Lewis posted a new activity comment 2 years, 3 months ago
Hi Nagella
To debug your code start by reading your code out loud. Do at least 2 iterations of your process.What we see is that you are calling InitSeed before generating each value.
Why is this a problem? Verification uses pseudo random. Each seed always produces the same sequence of values. For verification pseudo random is required so…[Read more]
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Jim Lewis replied to the topic Code Coverage with Aldec Riviera Pro in the forum OSVVM 2 years, 3 months ago
Hi Michael,
I may have specified an extra attribute during simulation. You can adjust for this by doing:
SetCoverageSimulateOptions "-acdb_cov sbm -cc_all"
But it still did not report anything, so I read more into the the Aldec Riviera-PRO reference manual:
> Riviera-PRO does not automatically recognize the finite state machines from code. The…[Read more] -
Jim Lewis replied to the topic Code Coverage with Aldec Riviera Pro in the forum OSVVM 2 years, 3 months ago
Hi Michael,
The intention is that it reports statemachine options. Maybe I am missing something in the scripts?You can set the specific options you want with SetCoverageAnalyzeOptions and SetCoverageSimulateOptions. The defaults for Riviera-PRO are as follows. I thought the “m” here is for statemachines.
`
SetCoverageAnalyzeOptions…[Read more] -
Jim Lewis replied to the topic Code Coverage with Aldec Riviera Pro in the forum OSVVM 2 years, 3 months ago
Hi Michael,
First a quick answer:
DoSetCoverageSimulateEnable true
before you build OSVVM libraries as well as anything else you don’t want coverage collected for.Why:
Currently when analyze is run for Riviera-PRO by default we do:
vcom -${VhdlVersion} -dbg -relax -work ${LibraryName} {*}${OptionalCommands} ${FileName}
The
-dbg
flag…[Read more] -
Jim Lewis wrote a new post 2 years, 3 months ago
Abstract
Some methodologies (or frameworks) are so complex that you need a script to create initial starting point for writing verification components, test cases, and/or the test harness. SystemVerilog + UVM […] -
Jim Lewis wrote a new post 2 years, 3 months ago
For some time now, OSVVM has been doing releases every month. Sometimes I talk about them, sometimes they just get posted to the downloads page.
Over the past several releases OSVVM has:
Im […]
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Jim Lewis replied to the topic Generate Statement Breaks UART RX VC in the forum OSVVM 2 years, 4 months ago
I have pushed the updated code to the main branch now.
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Jim Lewis replied to the topic Generate Statement Breaks UART RX VC in the forum OSVVM 2 years, 4 months ago
Hi Michael,
Unfortunately this impacts all OSVVM VC. So the same change is needed for the UartTx.Are you using sources from OSVVM.org or GitHub? I have updated the GitHub dev branch. I will update the main branch tomorrow. If you are using sources from OSVVM.org, I will update them too, otherwise, they will be updated when 2022.05 is…[Read more]
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Jim Lewis replied to the topic Generate Statement Breaks UART RX VC in the forum OSVVM 2 years, 4 months ago
Hi Michael,
Thanks for the long winded question – it gives me the information I need.It looks like the instance name is the same for all instances of the UART.
As a result statement that constructs the ReceiveFifo is connecting them all
together. Currently this:ReceiveFifo <= NewID("ReceiveFifo", ID, ReportMode => DISABLED) ;
It is…[Read more]
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Jim Lewis replied to the topic OSVVM and Cadence Xcelium in the forum OSVVM 2 years, 4 months ago
Hi Steve,
Thanks for the update. I have plans to test with Xcelium 22.03 soon.
Looking forward to seeing the results.Best Regards,
Jim -
Jim Lewis wrote a new post 2 years, 4 months ago
SynthWorks is continuing with our monthly instructor lead, on-line VHDL classes. With our “half day” on-line format, we do on-line classes right. Accelerate your learning pace of OSVVM. For additional cla […]
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Jim Lewis replied to the topic Synopsys VCS-MX in the forum OSVVM 2 years, 5 months ago
Hi Antonio,
You will need their latest service pack for VCS. I think there was one in October. The hot-fixes they were providing me for testing did not get integrated until shortly after the 2021.09 release.Best Regards,
Jim -
Jim Lewis commented on the post, OSVVM Scripting: One Script to Run them All 2 years, 5 months ago
Hi JJ,
Contributions are welcome.
Best Regards,
Jim -
Jim Lewis replied to the topic How to fit non-standard VCs/interfaces within the OSVVM framework in the forum OSVVM 2 years, 5 months ago
Hi Michael,
One thing you can do is in your verification component create a setting that controls whether PRBS is to be inverted or not. Then use SetModelOptions to change the settings. For AxiStream we have numerous settings and use an abstraction layer on top of SetModelOptions called SetAxiStreamOptions. For AxiStream the abstraction…[Read more] -
Jim Lewis replied to the topic randcovpoint in the forum OSVVM 2 years, 6 months ago
Please see GetRandPoint (its new name) in RandomPkg User Guide. There are also examples there.
Best Regards,
Jim -
Jim Lewis replied to the topic AxiStreamReceiver: Multiple Drivers on Transaction Record. in the forum OSVVM 2 years, 6 months ago
Hi Cols and Nico,
This brings up a bigger question, “how do we debug our simulations when something like this happens?”First observe the time at which something happens. Look at what transactions were running before that time.
If our simulator supports interactive debugging such as single step and/or breakpoint, then the following may help…[Read more]
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Jim Lewis replied to the topic AxiStreamReceiver: Multiple Drivers on Transaction Record. in the forum OSVVM 2 years, 6 months ago
Hi Cols and Nico,
Did you look at TbAxi4_Shared1.vhd? Each instance of the VC needs to have its own record. See TestCtrl_e.vhd in the same directory.Send me an email with your TestCtrl in it. It would probably be good to see your test harness also.
Best Regards,
Jim -
Jim Lewis wrote a new post 2 years, 6 months ago
Improve your verification capabilities with Open Source VHDL Verification Methodology (OSVVM).
OSVVM simplifies your FPGA and ASIC verification tasks by providing utility and model libraries. Using these free, […]
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