Activity – Jim Lewis – Open Source VHDL Verification Methodology

Jim Lewis replied to the topic Running example test-benches with GHDL in the forum OSVVM 3 years, 3 months ago

Are you running Ubuntu with the GCC build? Try either the mcode or lvvm. Unai setup CI for OSVVM. Prior to this I was testing OSVVM only on Windows 10 with 64 bit llvm. In testing we found that Ubuntu with GCC is not working for some items. I have not looked at the bugs, however, since it works for Ubuntu with mcode and lvvm and widows…[Read more]
Jim Lewis replied to the topic Vivado simulator and OSVVM in the forum OSVVM 3 years, 3 months ago

WRT OSVVM and xsim/Vivado. Here is the current update (July 2021):
I compiled all files on 2021.1. That was momentary good news. However, some packages do not work yet in simulation. In particular, AlertLogPkg. It needs a deep dive into root cause like I did for the AXI verification components in GHDL. It worked well in GHDL since I could find one…[Read more]
Jim Lewis replied to the topic Running example test-benches with GHDL in the forum OSVVM 3 years, 4 months ago

I should also note that the Virtual Transaction Interfaces (VC with suffix of Vti) use external names and GHDL does not support external names.
Jim Lewis replied to the topic Running example test-benches with GHDL in the forum OSVVM 3 years, 4 months ago

This is currently what I am running in the OSVVM libraries for regression:

build ../OsvvmLibraries
# Run Tests build ../OsvvmLibraries/UART/RunAllTests.pro build ../OsvvmLibraries/AXI4/AxiStream/RunAllTests.pro build ../OsvvmLibraries/AXI4/Axi4/RunAllTests.pro # Next one has failures in running tests build…[Read more]
Jim Lewis replied to the topic Running example test-benches with GHDL in the forum OSVVM 3 years, 4 months ago

I am running GHDL version: GHDL 2.0.0-dev (1.0.0.r292.g3807826b) [Dunoon edition]
This is from one of the nightly builds. All of 2021.06 compiles. All of 2021.06 simulates except Axi4Lite – Axi4 Full was updated to work with GHDL – so you can use that instead. The Axi4Lite updates will be coming later this year.
Jim Lewis wrote a new post 3 years, 6 months ago

In this second webinar of the VHDL-2019: Just the New Stuff series we will focus on enhancements to VHDL’s protected type capabilities.

Protected types simplify and abstract the construction of data […]
Jim Lewis wrote a new post 3 years, 7 months ago

IEEE 1076-2019, fondly referred to as VHDL-2019, was approved by IEEE RevCom in September 2019 and published in December 2019. The effort was supported mainly by VHDL users – from requirements definition to L […]
Jim Lewis wrote a new post 3 years, 8 months ago

Up your verification game with the latest from Open Source VHDL Verification Methodology (OSVVM).

OSVVM simplifies your FPGA and ASIC verification tasks by providing utility and model libraries. Using these […]
Jim Lewis wrote a new post 3 years, 8 months ago

Hi,
My name is Timothy Stotts, an FPGA and Embedded Systems engineer in upstate New York. There is an often less-discussed technique of adding vendor models to the VHDL test-bench for verifying the peripheral […]
Jim Lewis wrote a new post 3 years, 9 months ago

There is still space available in the next OSVVM Bootcamp: Advanced VHDL Testbenches and Verification class. Up level your VHDL verification skills.

In Europe, Enroll with FirstEDA at: […]
Jim Lewis wrote a new post 3 years, 10 months ago

OSVVM’s 2020.12 release introduces Virtual Transaction Interfaces (VTIs). VTIs allow us to connect to verification components (VCs) without using any ports or signals in the testbench framework. This cap […]
Jim Lewis started the topic QuestaSim SEGV Fatal fixed in 2020.12a in the forum OSVVM 3 years, 10 months ago

Testing for OSVVM 2020.12 release was done on RivieraPro 2020.10 and ModelSim 2020.01. Unfortunately I did not test with QuestaSim 2020.04 (my licenses are for a machine that I just finished setting up today).

There appears to be a subtle bug in QuestaSim that causes a SEGV Fatal when doing Burst Transfers (such as TbAxi4_MemoryBurst1). I…[Read more]
Jim Lewis wrote a new post 3 years, 10 months ago

2020 was quite a year.

While everything else was quite dark, OSVVM had a great 2020. Normally I travel for work around 75K air miles. 2020 none. This saved a lot of time. All of that time (and more) […]
Jim Lewis replied to the topic Synopsys VCS-MX in the forum OSVVM 3 years, 11 months ago

Hi Tim,
Ouch. Did you report the tool bug to Synopsys? Did they respond?

I would have to think about a work around. Maybe if generics were
added to the package to constrain the size of DataToModel, DataFromModel,
ParamToModel, and ParamFromModel – and they were sized to match the largest
item in the system, it should be ok – maybe after…[Read more]
Jim Lewis wrote a new post 3 years, 11 months ago

VHDL-93 (IEEE 1076-1993) created shared variables of an ordinary type as a temporary solution – which was noted in the standard document (aka LRM). VHDL-2000 (IEEE 1076-2000) created protected types as the onl […]
Jim Lewis wrote a new post 3 years, 11 months ago

Verification components have become an essential part of a structured VHDL environment. In OSVVM we implement verification components as an entity and architecture. This provides RTL engineers with a fam […]
Jim Lewis replied to the topic OSVVM and Cadence Xcelium in the forum OSVVM 3 years, 11 months ago

Hi Steve,
What we find is that users have more influence over vendors than I do. To be fair to them though, OSVVM has had numerous updates through COVID. One benefit of teaching on-line and not traveling is that I have had more time to work on OSVVM.

One of my goals is to get the OSVVM compile scripts working under Cadence Xcelium. If you…[Read more]
Jim Lewis wrote a new post 3 years, 11 months ago

The OSVVM 2020.10 release is finally out.
Why 2020.10?
Yes I realize it is now late November. So why 2020.10? In late October, the code was done and marked as 2020.10 with the expectation that the […]
- Torsten replied 3 years, 11 months ago
  
  One of the main things what OSVVM models differentiate from other available solutions is the extensive documentation. I like that very much.
  
  I remember closed source models which only have very little documentation and second, were written very poor. I used an FPGA-vendors eMMC model some years ago which was created in addition to the MMC controller unit we use. The model was only very basic and without doc, only the controller had some basic docs. After digging through the (Verilog) code I added some fundamental things like an associative array to allow data write/read checks coverage and assertions. Even with my little knowledge of (System) Verilog I was able to do that better.
Jim Lewis replied to the topic OSVVM 2020.08 New user experience in the forum OSVVM 4 years ago

Hi Richard,
I have been thinking about package that would have some global signaling events – such as
signal TestDone : integer_barrier; signal ResetDone : integer_barrier;

We could add something like:
signal TestErrorCount : integer ;

The idea is that if all tests had access to something like this, then it could be picked up automatically by…[Read more]
Jim Lewis replied to the topic What do you use for test suite orchestration? in the forum OSVVM 4 years ago

Hi Richard,
This is definitely in scope of a good discussion.

In 2020.08, OSVVM upgraded our scripting. Currently everything is TCL based, but the intent is to also have a BASH based executor of the scripting environment. One of the goals of the current approach is to create a simulation execution environment that is tool independent – ie:…[Read more]
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Jim Lewis

@jiml