Activity – Jim Lewis – Open Source VHDL Verification Methodology

Jim Lewis

Jim Lewis replied to the topic Question to the OSVVM community: how to approach the methodology, learning curve in the forum OSVVM 4 years, 9 months ago

To answer your questions:
1. How much time is needed?
In an instructor led class, you can learn OSVVM is 5 days. With our on-line classes, this translates to 10 on-line sessions – each session is approximately 2.5 hours of lecture (currently done via GoToMeeting) and 2.5 hours of lab (done on your own with support via email, phone, and…[Read more]
Jim Lewis wrote a new post 4 years, 9 months ago

Ready to go the next step with OSVVM? OSVVM training is available on-line.

Our on-line classes are live sessions with OSVVM author, Jim Lewis. Through SynthWorks, Mr Lewis has been offering VHDL tra […]
Jim Lewis commented on the post, Webinar: Creating an AXI4 Lite, Transaction Based VHDL Testbench with OSVVM 4 years, 9 months ago

Hi Cahit,
Here is the link to the recorded webinar. To get to it, you need to register with Aldec (who hosted the webinar).
https://www.aldec.com/en/support/resources/multimedia/webinars/2083

Best Regards,
Jim

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Jim Lewis wrote a new post 4 years, 10 months ago

I will be in Europe in March doing presentations on Open Source VHDL Verification Methodology (OSVVM) at the 2nd Workshop on Open-Source Design Automation (OSDA) and at the 5th Space FPGA Users Workshop […]
Jim Lewis replied to the topic Intelligent Coverage Random test generation in the forum OSVVM 4 years, 10 months ago

Hi Ken,
Yes and no. SV does not have this built into it or the UVM library.

OTOH, Accellera created a language that layers on top of other languages (I think VHDL too), called PSS (Portable Test and Stimulus Standard). Of course, it adds another layer of $$$$$ to your simulator budget.

Best Regards,
Jim
Jim Lewis commented on the post, Webinar: Creating an AXI4 Lite, Transaction Based VHDL Testbench with OSVVM 4 years, 10 months ago

Hi Cahit,
Yes it will be posted shortly at Aldec (the good folks who hosted the webinar).

Best Regards,
Jim

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Jim Lewis wrote a new post 4 years, 10 months ago

Over the last year, OSVVM has been growing rapidly. I was delighted to have the opportunity to present OSVVM papers at FPGA World (both Stockholm and Copenhagen) and at DVCon Europe in Munich. In addition, between […]
Jim Lewis wrote a new post 4 years, 10 months ago

Open Source VHDL Verification Methodology (OSVVM) simplifies your FPGA and ASIC verification tasks by providing utility and model libraries. Using these free, open source libraries you can create a simple, […]
- Cahit replied 4 years, 10 months ago
  
  I was wondering, if the webinar is recorded – and if yes, how to access it – for the OSVVM enthusiast, who unfortunately missed the event?
- Jim Lewis replied 4 years, 10 months ago
  
  Hi Cahit,
  Yes it will be posted shortly at Aldec (the good folks who hosted the webinar).
  
  Best Regards,
  Jim
  - Cahit replied 4 years, 10 months ago
    
    Looking forward to it 🙂
    Thanks Jim.
- Jim Lewis replied 4 years, 9 months ago
  
  Hi Cahit,
  Here is the link to the recorded webinar. To get to it, you need to register with Aldec (who hosted the webinar).
  https://www.aldec.com/en/support/resources/multimedia/webinars/2083
  
  Best Regards,
  Jim
Jim Lewis replied to the topic Coverage and sequences in the forum OSVVM 6 years, 4 months ago

Sure, it is easy. Sequences imply history. We create history explicitly just like RTL – by using clocked processes / flip-flops. Once you have history, this is just a simple cross product of selected current values and two previous values. WRT sampling, in OSVVM, we trigger on transaction completion using an explicit call to…
Jim Lewis replied to the topic Comparing Two std_logic_vectors in the forum VHDL 6 years, 4 months ago

Hi Torsten,In the IEEE VHDL-2008, there is only numeric_std_unsigned. There is no “signed” package. Jim
Jim Lewis wrote a new post 6 years, 8 months ago

Webinar Taming Testbench Messaging and Error Reporting with OSVVM’s Logs and Alerts.
Thursday April 5, 2018
Printing and error reporting in VHDL are tedious, yet necessary testbench tasks. Fortunately, Open S […]
Jim Lewis replied to the topic Possible bug in AlertLogPkg's Log procedure. in the forum OSVVM 6 years, 11 months ago

Hi Reuven,PathTail is intended to extract a component instance label from a PathName. For the string representation of a variable, signal, constant, or even entity name, you can indeed just use simple_name. I will update PathTail in the next revision so that it does not assume the name ends in a “:” and will return what you were…[Read more]
Jim Lewis wrote a new post 7 years, 2 months ago

Webinar OSVVM: ASIC Level Verification, Simple Enough for FPGAs. Thursday October 5, 2017
Just because your design is complex does not mean your testbench needs to be. With Open Source VHDL Verification […]
Jim Lewis replied to the topic Cannot compile the library with Modelsim 10.5b in the forum OSVVM 7 years, 3 months ago

I test with QuestaSim 10.5b so if you have the compile order correct, you should be fine.How did you compile it? Did you use the osvvm.do file? See: https://github.com/OSVVM/OSVVM/blob/master/osvvm.doDid you use the directions in the OSVVM_release_notes.pdf? See: https://github.com/OSVVM/OSVVM/blob/master/doc/osvvm_release_notes.pdfI note…[Read more]
Jim Lewis replied to the topic Limitation using MemoryPkg in the forum OSVVM 7 years, 4 months ago

Hi Eilert,In the 2008 standard it says:An implementation shall choose a representation for all floating-point types except for universal_real that conforms either to IEEE Std 754-1985 or to IEEE Std 854-1987; in either case, a minimum representation size of 64 bits is required for this chosen representation.I think this changed before 2008,…[Read more]
Jim Lewis replied to the topic Reporting ignored bins in the forum OSVVM 7 years, 6 months ago

Hi Roger,I just did a code review regarding AtLeast. Looking at the code, the AtLeast value is the maximum of the one specified by AddBins (the way I usually show to enter it) and the value specified by GenBin (also specified by a first integer value – but then also requires at least 4 parameters be used). Hence, if you specify both, you may be…[Read more]
Jim Lewis wrote a new post 7 years, 8 months ago

I am getting ready for the next session of Advanced Testbenches and Verification in UK and am looking forward to meeting another group of students.
Ready to improve your VHDL verification methodology? Come join […]
Jim Lewis replied to the topic Scoreboard Package Error in Questa in the forum OSVVM 7 years, 9 months ago

That unfortunately is a known bug. 10.4 brought some new cool features, but some how broke for the scoreboard in a way that I could not figure out how to work around. If you are just working with the primary releases, the following versions also exhibit the issue: 10.4, 10.4a, 10.4b, 10.4c. 10.3 was fine. 10.4d and 10.5 are fine. The…[Read more]
Jim Lewis replied to the topic Possible Error in "ScoreboardPkg User Guide.pdf" in the forum OSVVM 7 years, 9 months ago

Good catch. I updated the source document. Thanks.
Jim Lewis wrote a new post 8 years ago

2016.11a is a minor release. The only file that changed is VendorCovApiPkg_Aldec.vhd. There was a bug in one of the attributes that has been fixed and verified.
VendorCovApiPKg simplifies the connection […]
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Jim Lewis

@jiml