Activity – Jim Lewis – Open Source VHDL Verification Methodology

Jim Lewis

Jim Lewis wrote a new post 4 years, 5 months ago

It has been a busy summer for OSVVM. With the world working out of home offices, all of our training has shifted to on-line – which fortunately we started doing 7+ years ago. Not having to travel has freed up […]
Jim Lewis wrote a new post 4 years, 5 months ago

INTRODUCTION
Most people don’t think of VHDL as a verification language. However, with the Open Source VHDL Verification Methodology (OSVVM) utility and verification component libraries it is. Using OSVVM we can […]
Jim Lewis wrote a new post 4 years, 6 months ago

Up your VHDL verification game with the latest from Open Source VHDL Verification Methodology (OSVVM).

OSVVM 2020.07 focuses on Verification Components. AXI4 Full models were added. Axi4Lite, Axi […]
Jim Lewis wrote a new post 4 years, 7 months ago
Jim Lewis wrote a new post 4 years, 8 months ago

Ever wanted to encapsulate all the signals of an interface (such as AXI4Lite, I2C, …) into a single record only to be confounded by not being able to specify the direction for the elements of the record?

In t […]
Jim Lewis wrote a new post 4 years, 9 months ago

VHDL-2019 was approved by IEEE RevCom in September 2019 and published in December 2019. It was an effort supported mainly by VHDL users – from requirements definition to LRM writing. This is different from t […]
Jim Lewis wrote a new post 4 years, 9 months ago

Up your verification game with the latest from Open Source VHDL Verification Methodology (OSVVM).

OSVVM simplifies your FPGA and ASIC verification tasks by providing utility and model libraries. Using these […]
Jim Lewis replied to the topic UCIS / UCDB in the forum OSVVM 4 years, 9 months ago

Hi Michael,
Stefan Bauer out of the Mentor German office says he has written one. Last I knew, it is only available by request. I have made another inquiry about it.

Best Regards,
Jim
Jim Lewis replied to the topic Question to the OSVVM community: how to approach the methodology, learning curve in the forum OSVVM 4 years, 11 months ago

To answer your questions:
1. How much time is needed?
In an instructor led class, you can learn OSVVM is 5 days. With our on-line classes, this translates to 10 on-line sessions – each session is approximately 2.5 hours of lecture (currently done via GoToMeeting) and 2.5 hours of lab (done on your own with support via email, phone, and…[Read more]
Jim Lewis wrote a new post 4 years, 11 months ago

Ready to go the next step with OSVVM? OSVVM training is available on-line.

Our on-line classes are live sessions with OSVVM author, Jim Lewis. Through SynthWorks, Mr Lewis has been offering VHDL tra […]
Jim Lewis commented on the post, Webinar: Creating an AXI4 Lite, Transaction Based VHDL Testbench with OSVVM 4 years, 11 months ago

Hi Cahit,
Here is the link to the recorded webinar. To get to it, you need to register with Aldec (who hosted the webinar).
https://www.aldec.com/en/support/resources/multimedia/webinars/2083

Best Regards,
Jim

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Jim Lewis wrote a new post 5 years ago

I will be in Europe in March doing presentations on Open Source VHDL Verification Methodology (OSVVM) at the 2nd Workshop on Open-Source Design Automation (OSDA) and at the 5th Space FPGA Users Workshop […]
Jim Lewis replied to the topic Intelligent Coverage Random test generation in the forum OSVVM 5 years ago

Hi Ken,
Yes and no. SV does not have this built into it or the UVM library.

OTOH, Accellera created a language that layers on top of other languages (I think VHDL too), called PSS (Portable Test and Stimulus Standard). Of course, it adds another layer of $$$$$ to your simulator budget.

Best Regards,
Jim
Jim Lewis commented on the post, Webinar: Creating an AXI4 Lite, Transaction Based VHDL Testbench with OSVVM 5 years ago

Hi Cahit,
Yes it will be posted shortly at Aldec (the good folks who hosted the webinar).

Best Regards,
Jim

View Conversation
Jim Lewis wrote a new post 5 years ago

Over the last year, OSVVM has been growing rapidly. I was delighted to have the opportunity to present OSVVM papers at FPGA World (both Stockholm and Copenhagen) and at DVCon Europe in Munich. In addition, between […]
Jim Lewis wrote a new post 5 years ago

Open Source VHDL Verification Methodology (OSVVM) simplifies your FPGA and ASIC verification tasks by providing utility and model libraries. Using these free, open source libraries you can create a simple, […]
- Cahit replied 5 years ago
  
  I was wondering, if the webinar is recorded – and if yes, how to access it – for the OSVVM enthusiast, who unfortunately missed the event?
- Jim Lewis replied 5 years ago
  
  Hi Cahit,
  Yes it will be posted shortly at Aldec (the good folks who hosted the webinar).
  
  Best Regards,
  Jim
  - Cahit replied 5 years ago
    
    Looking forward to it 🙂
    Thanks Jim.
- Jim Lewis replied 4 years, 11 months ago
  
  Hi Cahit,
  Here is the link to the recorded webinar. To get to it, you need to register with Aldec (who hosted the webinar).
  https://www.aldec.com/en/support/resources/multimedia/webinars/2083
  
  Best Regards,
  Jim
Jim Lewis replied to the topic Coverage and sequences in the forum OSVVM 6 years, 6 months ago

Sure, it is easy. Sequences imply history. We create history explicitly just like RTL – by using clocked processes / flip-flops. Once you have history, this is just a simple cross product of selected current values and two previous values. WRT sampling, in OSVVM, we trigger on transaction completion using an explicit call to…
Jim Lewis replied to the topic Comparing Two std_logic_vectors in the forum VHDL 6 years, 6 months ago

Hi Torsten,In the IEEE VHDL-2008, there is only numeric_std_unsigned. There is no “signed” package. Jim
Jim Lewis wrote a new post 6 years, 10 months ago

Webinar Taming Testbench Messaging and Error Reporting with OSVVM’s Logs and Alerts.
Thursday April 5, 2018
Printing and error reporting in VHDL are tedious, yet necessary testbench tasks. Fortunately, Open S […]
Jim Lewis replied to the topic Possible bug in AlertLogPkg's Log procedure. in the forum OSVVM 7 years, 1 month ago

Hi Reuven,PathTail is intended to extract a component instance label from a PathName. For the string representation of a variable, signal, constant, or even entity name, you can indeed just use simple_name. I will update PathTail in the next revision so that it does not assume the name ends in a “:” and will return what you were…[Read more]
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Jim Lewis

@jiml