Jim Lewis

Hi Nagella,
I typically use an active low reset (ie: 0 when active). Did I guess wrong in your case?
Let me be a little more abstract. Lets assume the constant ACTIVE has the value that
reset has when it is active.

process
variable RV:RandomPType;
variable b:std_logic_vector( 7 downto 0);
begin
RV.Initseed(RV’instance_name);
-- i…[Read more]

Hi Omaima,
First, I should note you are using the older version of CoveragePkg that has a protected type interface. I suggest that you upgrade to the newer version that has a singleton interface. Please see CoveragePkg_user_guide.pdf in the OsvvmLibraries/Documentation.

Coverage is a data structure. Calls are done in order and items…[Read more]

Hi Nagella
To debug your code start by reading your code out loud. Do at least 2 iterations of your process.

What we see is that you are calling InitSeed before generating each value.

Why is this a problem? Verification uses pseudo random. Each seed always produces the same sequence of values. For verification pseudo random is required so your…[Read more]

Hi Michael,
I may have specified an extra attribute during simulation. You can adjust for this by doing:
SetCoverageSimulateOptions "-acdb_cov sbm -cc_all"

But it still did not report anything, so I read more into the the Aldec Riviera-PRO reference manual:
> Riviera-PRO does not automatically recognize the finite state machines from code. The…[Read more]

Hi Michael,
The intention is that it reports statemachine options. Maybe I am missing something in the scripts?

You can set the specific options you want with SetCoverageAnalyzeOptions and SetCoverageSimulateOptions. The defaults for Riviera-PRO are as follows. I thought the “m” here is for statemachines.
`
SetCoverageAnalyzeOptions…[Read more]

Hi Michael,
First a quick answer:
Do SetCoverageSimulateEnable true before you build OSVVM libraries as well as anything else you don’t want coverage collected for.

Why:
Currently when analyze is run for Riviera-PRO by default we do:
vcom -${VhdlVersion} -dbg -relax -work ${LibraryName} {*}${OptionalCommands} ${FileName}

The -dbg flag…[Read more]

I have pushed the updated code to the main branch now.

Hi Michael,
Unfortunately this impacts all OSVVM VC. So the same change is needed for the UartTx.

Are you using sources from OSVVM.org or GitHub? I have updated the GitHub dev branch. I will update the main branch tomorrow. If you are using sources from OSVVM.org, I will update them too, otherwise, they will be updated when 2022.05 is…[Read more]

Hi Michael,
Thanks for the long winded question – it gives me the information I need.

It looks like the instance name is the same for all instances of the UART.
As a result statement that constructs the ReceiveFifo is connecting them all
together. Currently this:

ReceiveFifo <= NewID("ReceiveFifo", ID, ReportMode => DISABLED) ;

It is…[Read more]

Hi Steve,
Thanks for the update. I have plans to test with Xcelium 22.03 soon.
Looking forward to seeing the results.

Best Regards,
Jim

Hi Antonio,
You will need their latest service pack for VCS. I think there was one in October. The hot-fixes they were providing me for testing did not get integrated until shortly after the 2021.09 release.

Best Regards,
Jim

Hi Michael,
One thing you can do is in your verification component create a setting that controls whether PRBS is to be inverted or not. Then use SetModelOptions to change the settings. For AxiStream we have numerous settings and use an abstraction layer on top of SetModelOptions called SetAxiStreamOptions. For AxiStream the abstraction…[Read more]