Jim Lewis

Hi Hassan,
For the OSVVM MemoryPkg, see FileReadH and FileReadB as well as their counter parts FileWriteH and FileWriteB.

For simulation based RAMS, you want to be using OSVVM’s MemoryPkg as it creates sparse memory data structures – ie it only allocates blocks of memory (in 1 K chunks) if you write to a particular location.

Best Regards,
Jim

Hassan,
The way languages get enhanced is for people like yourself to go to the working group web page and make proposals and contribute to the development effort.

For VHDL, the appropriate place to make proposals is at: https://gitlab.com/IEEE-P1076/VHDL-Issues/-/issues/

VHDL in particular is a volunteer driven standard. Hence, it is…[Read more]

2024.07 updates CreateClock. They are breaking changes – meaning the way clock starts up is different. There was alot of unneeded complexity that was part of the old CreateClock that has been minimized – while still keeping clock changing at simulation cycle 0 (aka delta cycle 0).

If you want to preview it, see the Dev branch. Nominally it…[Read more]

Just a quick note, release 2024.07 will have a CreateJitterClock:

`
procedure CreateJitterClock (
signal Clk : inout std_logic ;
signal CoverID : inout CoverageIdType ;
constant Name : in string ;
constant Period : in time ;
constant DutyCycle : in real := 0.5 ;…[Read more]

The IEEE group that works on EDA standards in general and spawns out groups like the IEEE 1076 WG is named DASC. You can find their website here: https://dasc.org/ You can certainly work through them to form such a working group.

You should be able to surround the process with
`– synthesis translate_off
process …
end process;
— synthesis translate_on

Hi Lars,
OSVVM has an InterruptHandler.vhd in OsvvmLibraries/Common/Src. It handles switching records for you. When there is no interrupt pending, it connects the transaction record of TransRec to the AddressBus VC (such as Axi4Manager or Axi4LiteManager). When an interrupt is pending it connects the InterruptRec to the AddressBusVC.

The…[Read more]

Hi Hassan,
It is part of VHDL-2019. It is called Conditional Analysis. I have heard that vendors support it in older revisions.

For details, see my presentation, VHDL-2019: Just the New Stuff Part 1: Interfaces, Conditional Analysis, File IO, and Environment. I did this through Aldec as one of their events. You should be able to register…[Read more]

Hi Lars,
OSVVM has an InterruptHandler.vhd in OsvvmLibraries/Common/Src. It handles switching records for you. When there is no interrupt pending, it connects the transaction record of TransRec to the AddressBus VC (such as Axi4Manager or Axi4LiteManager). When an interrupt is pending it connects the InterruptRec to the AddressBusVC.

The…[Read more]

Hi Steve,
No documentation yet. Set the test case that is for now in TestStandAlone/Tb_xMii.vhd.

The VC are streaming interfaces that accept SendBurst and GetBurst.

Best Regards,
Jim

Hi Hassan,
The 2024.07 release will have a limited set of predefined events added to OSVVM. One of them will signal that the test case has initialized the VC and the VC can start handler type operation.

I have an initial proof of concept test case working at this point and expect to release it to the Dev branch sometime soon.

In addition,…[Read more]

> What is the meaning of writing something like this: GenBin(2,10,2)

If this is the only GenBin for a given coverage model, this does not change anything.

Note the coverage model that I edited into the previous discussion for the AxiStreamTransmitter. If I instead did:
AddBins (BurstCov.BurstDelayCov, 80, GenBin(2,8,2)) ; -- 80% Small…[Read more]

> Q1. When the GenBin has 3 numbers, why does it always end with 1? This means that we are creating a single bin that has the specified range? This means that any integer can occur in that range with equal probability?

The third parameter indicates how many bins to split a range into. As you observed, this puts it all in one bin. It is indeed…[Read more]

There was. It was removed as it did not work in one of the vendors. I will need to add it back.

Hi Hassan
The AXI interface has a number of optional signals. How to handle these is the interesting proposition. Their width can be configured. The current VC leaves them unconstrained. This means they have to be connected, even if unused and connected to a 0 width std_logic_vector(0 downto 1).

That said, can their impact be minimized.…[Read more]

This is just the VHDL signal use model when reading it after assigning it in a process. Since RTL does not allow wait for 0 ns, it is limited to testbenches.

Verilog assignments have the same sort of issue.

Hi Ajeetha,
Next time please provide a complete testable example, such as I have provided below. Try running this.

library osvvm ;
context osvvm.OsvvmContext ;
use osvvm.ScoreboardPkg_int.all ;

ControlProc :…[Read more]

Do:
stim : process
begin
SB_int <= NewID("COUNT_SB");
wait for 0 ns; -- let SB_int to update
report ("SB_int: " & integer'image(SB_int.Id));
i_up_or_down <= '0';
push(SB_int, 2);
. . .

Hi Ajeetha,
Nope. That is integer’left.

Put a “wait for 0 ns” before reading the signal. That allows a simulation cycle to go by and the signal to update to the value assigned by NewID.

Jim