Jim Lewis
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Jim Lewis replied to the topic OSVVM and Cadence Xcelium in the forum OSVVM 2 years, 2 months ago
Hi Steve,
I did some testing with Cadence over the last week. Looks like the 2022.08 updates to memory pkg broke some things. On the dev branch of OSVVM, I moved MemoryPkg_c.vhd back to the 2022.06 version.It also looks like Cadence is failing the singleton tests in CoveragePkg. I need to try to find root cause as the singleton tests in…[Read more]
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Jim Lewis replied to the topic Verification with SystemVerilog or VHDL in the forum OSVVM 2 years, 2 months ago
Hi Oliver,
> Above all, there is no SystemVHDL as a complement to the SystemVerilog
Renaming Verilog to SystemVerilog is simply marketing. Just asking that question demonstrates the brilliance it.OSVVM provides VHDL with “SystemVerilog + UVM” verification capabilities including Transaction Level Modeling, Constrained Random, Functional…[Read more]
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Jim Lewis replied to the topic Custom VC for image-sensor interface in the forum OSVVM 2 years, 2 months ago
Hi Thomas,
I try to divide the concerns into what must be done for every transaction and what is stable for a long period of time. Things that are stable for a long period of time can be set with SetModelOptions.The error injection probability is a candidate for SetModelOptions.
You may wish for things like Image Width, Height, Color Depth,…[Read more]
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Jim Lewis wrote a new post 2 years, 3 months ago
As I was writing the blog about the 2022.10 Multiple Verification Component example, my focus was drawn to the issue, “How do I call transactions that iterate across an array of verification components?” […]
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Jim Lewis replied to the topic Memory leak or not ? in the forum VHDL 2 years, 3 months ago
Memory leak. I do not think the simulators are able to handle this for you.
I should note general VHDL questions like this may get a response faster on StackOverflow, however, I have indeed encountered this one and know a couple of solutions.
The simplest that I have seen, but not used (so it may have flaws) is:
`vhdl
function my_function(obj…[Read more] -
Jim Lewis replied to the topic Passing arguments to simulation run script in the forum OSVVM 2 years, 3 months ago
Hi Anna,
Sorry, some how while answering your questions on GitHub, I missed your question here.For all others, here is a summary of the resolution of Anna’s question.
With the 2022.10 update, the same actions can be accomplished with the following call to simulate. Note while the items in square brackets are optional, if you use generic…[Read more]
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Jim Lewis wrote a new post 2 years, 3 months ago
Several times now I have been asked how to use multiple OSVVM VC, like a UART, in a simulation. This should be simple, however, there are a couple of VHDL and OSVVM got-yas.
For the 2022.10 release, I prepared […]
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Jim Lewis wrote a new post 2 years, 3 months ago
Summary of recent changes in OSVVM.
Added Ethernet Phy and MAC verification components for GMII, RGMII, MII, RMII
Added interrupt handler that supports any verification component that uses the […] -
Jim Lewis wrote a new post 2 years, 3 months ago
Don’t miss your chance to express what verification approach you use for FPGAs (OSVVM)
This is the first public survey I have seen. Others have been done by random selection and invitation only.
Survey is here
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Jim Lewis wrote a new post 2 years, 3 months ago
On GitHub Issues, I had the following question, “With OSVVM scripting (.pro), is there a way to specify testbench generics, waveform files, and length of time to run a simulation.”
So lets take a look at these. […]
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Jim Lewis started the topic Questa-Intel & Reports in the forum OSVVM 2 years, 4 months ago
Recently due to some issue reports, I had a look at Questa-Intel 2021.02. When I ran it, it would not create proper OSVVM log and html log messages – much of the information was missing.
The first thing I noticed is that it started up with two windows instead of just the GUI:
So I consulted with a friend of mine to see if he knew what the…[Read more]
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Jim Lewis started the topic OSVVM, Questa – Fails to Compile OSVVM in the forum OSVVM 2 years, 4 months ago
In the Questa – Intel 2022.0X version, the osvvm library was removed, but the library mapping for osvvm still remains in the ini file at /questa_fse/modelsim.ini. This unfortunately prevents OSVVM from compiling.
The only way I have found to fix it is to comment out the mapping in the ini file. To do this, simply put a ‘;’ as the first…[Read more]
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Jim Lewis started the topic OSVVM & Questa – Calls to PushBurstRandom in the forum OSVVM 2 years, 4 months ago
For Questa 2021.02, there is an issue with it being able to simulate calls to PushBurstRandom and CheckBurstRandom with an integer FirstWord value:
procedure PushBurstRandom (
[Read more]
constant Fifo : in ScoreboardIdType ;
constant FirstWord : in integer ;
constant Count : in integer ;
constant FifoWidth : in… -
Jim Lewis replied to the topic OSVVM and Cadence Xcelium in the forum OSVVM 2 years, 4 months ago
Hi Steve,
Checking out the current version is on my todo list. The Xcelium team has our full regression suite so I would expect it all to be working at this point.I don’t think I introduced anything in the more current release that would cause Xcelium to stop working. But again, I hopefully will have a moment to test soon.
Best Regards,
Jim -
Jim Lewis replied to the topic .gitmodules File in the forum OSVVM 2 years, 4 months ago
Hi Ryan,
Thanks. It will be updated no later than the 2022.10 release.Best Regards,
Jim -
Jim Lewis replied to the topic Synopsys VCS-MX in the forum OSVVM 2 years, 4 months ago
Hi Antonio,
I should be able to look into it shortly too. Also if it is a TCL error, you may need to update your TCL version.Cheers,
Jim -
Jim Lewis wrote a new post 2 years, 5 months ago
Summary of recent changes in OSVVM:
Scripts updated for better signaling to continuous integration (CI) tools
MemoryPkg updated to remove 31 bit limitation and support storage policies.
Reports keep […]-
Ha, very nice.
In my current system test bench of a AXI-QDMA Interface I model memory using my own dictionary implementation. First I used plain `std_logic_vector`, but it became slower & slower with increasing writes to new addresses in the dict. Then I’ve remembered that integers are “faster” than values with 9-state logic. So I’ve done something similar to your MemoryPkg, using an `integer_vector(0 to 1)` to store 64-bit wide `std_logic_vector` values, and also using integers for the address in the dictionary.
I’ve looked into an older version of your MemoryPkg before, which was limited to 31 bit – which was the reason for my own memory implementation. Now that this restriction is gone, it’s maybe finally time to try OSVVMs MemoryPkg.
Greetings,
Torsten
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Jim Lewis replied to the topic Standard messaging feature in OSVVM? in the forum OSVVM 2 years, 5 months ago
See OSVVM’s AlertLogPkg for today’s answer to this question
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Jim Lewis replied to the topic 31 bit maximum data width for memory package in the forum OSVVM 2 years, 6 months ago
Hi Michael,
New version is release as 2022.08. MemoryPkg is now a generic package.Instance MemoryPkg (and MemoryPkg_X) support any number of bits. If there is an X or U in a bit in the data word, only that bit will read back as an X or U (respectively).
Instance MemoryPkg_NoX supports any number of bits. All meta values (UXZW-) are…[Read more]
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Jim Lewis replied to the topic New to OSVVM / problem running the example in the forum OSVVM 2 years, 6 months ago
Hi Phil,
I just installed 2020.3 Microsemi edition. I have a Libero Silver 1 Yr DiskID NL License. It runs the demo fine.With some of the older OSVVM versions a space in the path was problematic, however, that was addressed in a previous release.
Best Regards,
Jim - Load More