Jim Lewis

Hi Adam,
I am not sure what that means. What are you trying to do? In Axi4Lite, strb is a byte strobe that indicates the corresponding 8 bits is part of the write. The strb will be active when Valid is active. This may be multiple clock cycles if Ready is not also active.

Does the dpRAM only accept full 32 bit writes? Maybe this device…[Read more]

Hi Adam,
The AxiStreamTransmitter and AxiStreamReceiver both have randomization in them. There is a corresponding test case that has good examples in it, TbStream_SendGetRandom1.vhd. You can find it in OsvvmLibraries/AXI4/AxiStream/TestCases. It was just updated (meaning just before this post) to better show the different use models for…[Read more]

Oops. It took me until now to push the files to GitHub properly.

Agreed that SetDebugMode is enough for what you are doing. SetInteractiveMode = SetDebugMode + SetLogSignals + Stop Simulation when analyze or simulate error occurs.

I use SetInteractiveMode false when running a set of simulations in CI or as a regression as I want to see results from all tests, but SetInteractiveMode when debugging.

Hi Adam,
Adding random delays is a work in progress. I am posted about updates in https://osvvm.org/forums/topic/learning-osvvm-with-axi4#post-2209.

Best Regards,
Jim

Hi Adam,
I just pushed a new version of Axi4Manager.vhd with random delays. They maintain backward compatibility, and hence, you have to turn on the randomization features. No documentation yet. I still have to add random delays to Axi4Memory and Axi4Subordinate – I also need to add them to the VTI versions of the VC. Also the initial delay…[Read more]

Hi Jason,
Resolution functions are a VHDL-1987 feature. So Ashenden’s VHDL Designers Guide should have a good description of them. I will describe them briefly here too.

In VHDL-2008, element based resolution functions were extended to support array objects. So std_logic_vector is now defined as:
subtype std_logic_vector is (resolved)…[Read more]

Hi Adam,
WRT randomness in dispatching each channel, that is what I am currently working on. I added it to AxiStream in a Beta form in an earlier OSVVM release – it has changed some on the Dev branch. I will be adding it to Axi4 VC next. Each channel will be independent, so a write data should randomly happen prior to write address, as will…[Read more]

Hi Jamie,
The working library (denoted as work in VHDL) is the library into which you are currently compiling. Hence, the OSVVM packages use the name work to reference items (use work.TranscriptPkg.all).

Currently VHDL context clauses do not allow the usage of the library work. Hence, you see the usage of OSVVM there.

Diving a little…[Read more]

Hi Adam,
I have added some beta features to the 2023.04 release to see if we can address this better. As a Beta feature, there is no documentation yet – as it may change. See AxiStream/TestCases/TbStream_SendGetRandom1.vhd.

Best Regards,
Jim

Hi Adam,
Not yet. Are you interested in doing a pull request against TbUtilPkg?

Best Regards,
Jim

LibraryUnit in this case is the name which you used with simulate, hence, either the name of your testbench or configuration that runs your testbench. Often, I try to make this the same as the TextCaseName, but it does not have to be.

In VHDL, LibraryUnit is an analyzed Design Unit and from the LRM,

A design unit is
either an entity…

[Read more]

Hi Adam,
Currently the features that control these is described on pages 26 and 27 of the AxiStream_user_guide.pdf in OsvvmLibraries/Documentation. There are two controls for this:
RECEIVE_READY_BEFORE_VALID – this is true by default and allows TReady to be generated even if TValid is not asserted.
RECEIVE_READY_DELAY_CYCLES – Number of…[Read more]

Is that the Questa Intel edition or another edition?

Hi Anna,
Two thoughts on that.

First, there is no need for an expected SLVERR to be an actual test case error. The following is from p37 of the Axi4_VC_user_guide.pdf that is in the documentation repository:

By default, the expected value for BRESP and RRESP are OKAY. When testing a subordinates response to an incorrect address, a SLVERR is…[Read more]

Hi Oliver,
There is an OSVVM SPI model at: https://github.com/noasic/SPI

My long term plan is to clone it. It is a candidate for inclusion in OSVVM.

Best Regards,
Jim