Activity – Jim Lewis – Open Source VHDL Verification Methodology

Jim Lewis wrote a new post 3 years, 6 months ago

VHDL + Open Source VHDL Verification Methodology (OSVVM) is great for verification and is a competitor to SystemVerilog + UVM. Especially in the FPGA space where VHDL is the dominant language (see the 2020 […]
Jim Lewis replied to the topic OSVVM and Cadence Xcelium in the forum OSVVM 3 years, 7 months ago

Hi Steve,
A quick update. I am working with Cadence on Xcelium. Things are looking up. I should have more news on this shortly.

I have provided them with the full OSVVM regression suite. I am optimistic, but I don’t know the time frame for them to update Xcelium.
Jim Lewis replied to the topic Synopsys VCS-MX in the forum OSVVM 3 years, 7 months ago

A quick update. I am working with Synopsys on VCS. Things are looking up. I should have more news on this shortly.
Jim Lewis replied to the topic Running example test-benches with GHDL in the forum OSVVM 3 years, 8 months ago

Found it!

Apparently the mcode version of GHDL errors out if you subtract 1 from an uninitialized integer.
All other simulators are ok with this. OTOH, it was easy enough to fix. So there is
now a fix in the 2021.07 release. It is on GitHub now. It will be on OSVVM.org
shortly
Jim Lewis replied to the topic Running example test-benches with GHDL in the forum OSVVM 3 years, 9 months ago

Are you running Ubuntu with the GCC build? Try either the mcode or lvvm. Unai setup CI for OSVVM. Prior to this I was testing OSVVM only on Windows 10 with 64 bit llvm. In testing we found that Ubuntu with GCC is not working for some items. I have not looked at the bugs, however, since it works for Ubuntu with mcode and lvvm and widows…[Read more]
Jim Lewis replied to the topic Vivado simulator and OSVVM in the forum OSVVM 3 years, 9 months ago

WRT OSVVM and xsim/Vivado. Here is the current update (July 2021):
I compiled all files on 2021.1. That was momentary good news. However, some packages do not work yet in simulation. In particular, AlertLogPkg. It needs a deep dive into root cause like I did for the AXI verification components in GHDL. It worked well in GHDL since I could find one…[Read more]
Jim Lewis replied to the topic Running example test-benches with GHDL in the forum OSVVM 3 years, 9 months ago

I should also note that the Virtual Transaction Interfaces (VC with suffix of Vti) use external names and GHDL does not support external names.
Jim Lewis replied to the topic Running example test-benches with GHDL in the forum OSVVM 3 years, 9 months ago

This is currently what I am running in the OSVVM libraries for regression:

build ../OsvvmLibraries
# Run Tests build ../OsvvmLibraries/UART/RunAllTests.pro build ../OsvvmLibraries/AXI4/AxiStream/RunAllTests.pro build ../OsvvmLibraries/AXI4/Axi4/RunAllTests.pro # Next one has failures in running tests build…[Read more]
Jim Lewis replied to the topic Running example test-benches with GHDL in the forum OSVVM 3 years, 9 months ago

I am running GHDL version: GHDL 2.0.0-dev (1.0.0.r292.g3807826b) [Dunoon edition]
This is from one of the nightly builds. All of 2021.06 compiles. All of 2021.06 simulates except Axi4Lite – Axi4 Full was updated to work with GHDL – so you can use that instead. The Axi4Lite updates will be coming later this year.
Jim Lewis wrote a new post 3 years, 11 months ago

In this second webinar of the VHDL-2019: Just the New Stuff series we will focus on enhancements to VHDL’s protected type capabilities.

Protected types simplify and abstract the construction of data […]
Jim Lewis wrote a new post 4 years ago

IEEE 1076-2019, fondly referred to as VHDL-2019, was approved by IEEE RevCom in September 2019 and published in December 2019. The effort was supported mainly by VHDL users – from requirements definition to L […]
Jim Lewis wrote a new post 4 years, 1 month ago

Up your verification game with the latest from Open Source VHDL Verification Methodology (OSVVM).

OSVVM simplifies your FPGA and ASIC verification tasks by providing utility and model libraries. Using these […]
Jim Lewis wrote a new post 4 years, 1 month ago

Hi,
My name is Timothy Stotts, an FPGA and Embedded Systems engineer in upstate New York. There is an often less-discussed technique of adding vendor models to the VHDL test-bench for verifying the peripheral […]
Jim Lewis wrote a new post 4 years, 1 month ago

There is still space available in the next OSVVM Bootcamp: Advanced VHDL Testbenches and Verification class. Up level your VHDL verification skills.

In Europe, Enroll with FirstEDA at: […]
Jim Lewis wrote a new post 4 years, 3 months ago

OSVVM’s 2020.12 release introduces Virtual Transaction Interfaces (VTIs). VTIs allow us to connect to verification components (VCs) without using any ports or signals in the testbench framework. This cap […]
Jim Lewis started the topic QuestaSim SEGV Fatal fixed in 2020.12a in the forum OSVVM 4 years, 3 months ago

Testing for OSVVM 2020.12 release was done on RivieraPro 2020.10 and ModelSim 2020.01. Unfortunately I did not test with QuestaSim 2020.04 (my licenses are for a machine that I just finished setting up today).

There appears to be a subtle bug in QuestaSim that causes a SEGV Fatal when doing Burst Transfers (such as TbAxi4_MemoryBurst1). I…[Read more]
Jim Lewis wrote a new post 4 years, 3 months ago

2020 was quite a year.

While everything else was quite dark, OSVVM had a great 2020. Normally I travel for work around 75K air miles. 2020 none. This saved a lot of time. All of that time (and more) […]
Jim Lewis replied to the topic Synopsys VCS-MX in the forum OSVVM 4 years, 4 months ago

Hi Tim,
Ouch. Did you report the tool bug to Synopsys? Did they respond?

I would have to think about a work around. Maybe if generics were
added to the package to constrain the size of DataToModel, DataFromModel,
ParamToModel, and ParamFromModel – and they were sized to match the largest
item in the system, it should be ok – maybe after…[Read more]
Jim Lewis wrote a new post 4 years, 4 months ago

VHDL-93 (IEEE 1076-1993) created shared variables of an ordinary type as a temporary solution – which was noted in the standard document (aka LRM). VHDL-2000 (IEEE 1076-2000) created protected types as the onl […]
Jim Lewis wrote a new post 4 years, 4 months ago

Verification components have become an essential part of a structured VHDL environment. In OSVVM we implement verification components as an entity and architecture. This provides RTL engineers with a fam […]
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Jim Lewis

@jiml