Jim Lewis

More direct control refers to output formatting when a check passes or fails.

> From my knowledge, VHDL already contains resolution functions for scenarios where something has multiple drivers. So are new functions required to resolve records with multiple drivers?
VHDL has a resolution function for std_ulogic named resolved. Its non-driving element is ‘Z’. Its default value is ‘U’. If you do not initialize it, then…[Read more]

Hi Brad,
Cool. If we end up needing that, it will be added. However, that said, I am curious as to why it is needed. Normally variable expansion is done in the calling scripts.

So if I do:
SetExtendedSimulateOptions "-dbg -t 0 -ieee_nowarn -dataset {./sim} -datasetname {sim} -loadvhpi $aldec/bin/aldec_matlab_cosim.dll:ml2hdl"

Then I…[Read more]

Hi Ajeetha,
Since you are creating a code generator I recommend that when it uses ScoreboardIDType that it always uses a selected path that includes the library and package as that way if people using the generated code add to it they too will not have any issues – and they will have a safe example from which to template.

If your generator…[Read more]

Hi Ajeetha,
WRT scoreboards, there are no known issues with either GHDL or NVC.

There is a subtle VHDL thing with using or referencing multiple generic packages that declare a type – such as ScoreboardIDType that is declared in ScoreboardGenericPkg.

If you reference only one Scoreboard package instance, such as ScoreboardPkg_slv, then the…[Read more]

The DelayCoverage models divide a transfer into segments that are BurstLength in length. For beats (transfers within that burst length) there is BeatDelay between each item transferred on the interface. After BurstLength there is BurstDelay before the next item is transferred. Each of BurstLength, BeatDelay, and BurstLength is randomized using…[Read more]

> Q2. Why does one need “Alert” functions when “Affirm” functions also exists?
Alert is for parameter checks – like is max >= min. These are properties that if violated, the design (or test case) is broken.

Affirm is for self checking. Each check is counted. A test quality is a function of the number of checks and we report that.

>…[Read more]

What you find in the documentation is what is what is officially supported.

The scoreboard package was released to our classes in 2006. The AlertLog capability was added in 2015. So there is some history there. Certainly doing

Get(TRec, Data) ;
expectedData := pop(SbID) ;
AffirmIfEqual(TbID, Data, expectedData) ;

Is very similar…[Read more]

The Axi4Manager has a TransactionDispatcher, which receives transactions from the Test Sequencer (TestCtrl) and dispatches these out to interface handlers (such as WriteAddressHandler). The interface handlers connect to the DUT and represent independently running pieces of the VC. The communication between the TransactionDispatcher and…[Read more]

Hi Brad,
Short answer: yes you must run either simulate or RunTest to get the coverage reports

Behind the scenes when simulate finishes it saves the code coverage data base. When a test suite finishes, the code coverage from each test case is merged together. When the build finishes, it merges together the coverage from each test suite and…[Read more]

Hi Hassan
OSVVM VC creates an AlertLogID for different classes of checkers. It is helps tracking the sources of errors – hence accelerates debug. In your own VC, you can get by with just a ModelID.

Params is another singleton data structure that holds settings for the VC. It is setup like a generalized union of values.

Best Regards,
Jim

Hi Brad,
First thing to determine is what switches you need set to vcom and vsim.

If you look at the log or html log, you can determine what OSVVM is currently doing – or you can read the OsvvmProjectScripts.tcl (older releases) or OsvvmScriptsCore.tcl (renamed in 2024.05 to support future refactoring).

You can use SetExtendedAnalyzeOptions…[Read more]

Yes. The long term plan is to add more extensive protocol violation checks it Axi4Monitor. I think a number of them are about checking that an AXI4 manager always composes a complete transaction. I am not sure the value of them if you are developing an Axi4Subordinate (formerly known as slave).

Don’t despair too much at least for Xilinx I think it will be coming. They have implemented the VHDL-2019 feature called interfaces – which is a record + mode view. A mode view specifies the IO direction of each element the record. With this, they will need to support it through all of their tools, such as Platform and Block Designer. I…[Read more]

I am not sure how Xilinx deals with this, however, for any composite port, VHDL allows you to map composites (records or arrays) element by element, below done as a formal:
`————————————————————
Manager_1 : Axi4Manager
————————————————————
port map (
–…[Read more]

AXI3 should be supported by the AXi4 VC. I looked at either AHB or APB – they could be quick to implement. The harder part is verifying the VC.

Currently high priority on my list is Avalon MM and Avalon Stream.

> Does OsvvmLibraries contain test plan that describes what specific tests exist?

I have not published one. I have it in my notebook. It would be a good idea to publish it.

> These TCL commands TestSuite, RunTest and SkipTest appear to be defined in the OsvvmProjectScripts.tcl. There are other commands like build, analyze, include for which…[Read more]

> Does OsvvmLibraries contain test plan that describes what specific tests exist?

I have not published one. I have it in my notebook. It would be a good idea to publish it.

> These TCL commands TestSuite, RunTest and SkipTest appear to be defined in the OsvvmProjectScripts.tcl. There are other commands like build, analyze, include for which…[Read more]